# AND and OR: the price of not inverting

*Why the friendly gates cost an extra stage*

Because every static CMOS gate is naturally inverting, AND is built as a NAND followed by an inverter and OR as a NOR followed by an inverter, so each non-inverting gate costs six transistors and two stages of delay instead of a NAND or NOR's four transistors and one stage.

Group: From logic to silicon
URL: https://digiwleea.wleeaf.dev/learn/and-or-build/

You have the inverting gates: [NAND and NOR](https://digiwleea.wleeaf.dev/learn/nand-nor-build/), four transistors each. But logic is usually written with plain **AND** and **OR**. Where are their transistor circuits? The surprising answer is that CMOS has no direct, single-stage AND or OR at all. To see why, and what it costs, we need one fact about static CMOS gates.

## Every static CMOS gate is naturally inverting

Look back at what a pull-down does: an NMOS network can only pull the output *down* toward `0`, and it conducts for exactly the input combinations it detects. So whenever the condition it detects is true, the output is forced *low*. The output is therefore the **logical inverse** of the condition the network detects. Every static CMOS gate carries that built-in bubble. That is precisely why the cheap, natural gates are the *inverting* ones (NAND, NOR, NOT): the inversion comes for free from the physics. A plain AND or OR has to *undo* that inversion, and undoing it costs an extra gate.

> **KEY:** The natural CMOS gates invert. NAND, NOR, and NOT are cheap because the inversion is free. AND and OR are their non-inverting cousins, so each is built by canceling the inversion with a second gate: **AND = NAND then NOT**, **OR = NOR then NOT**.

## AND = NAND then NOT

A [NAND](https://digiwleea.wleeaf.dev/learn/nand-nor-build/) computes `NOT(A AND B)`. Invert that with a [NOT](https://digiwleea.wleeaf.dev/learn/inverter-build/) and the two inversions cancel, leaving `A AND B`. So a CMOS AND is literally a NAND with an inverter bolted onto its output: four transistors for the NAND plus two for the inverter, **six transistors** and **two stages** of delay.

```
A AND B = NOT( NOT(A AND B) ) = NOT(A NAND B)
```

_Circuit diagram: AND built as a NAND feeding an inverter. The NAND does the work; the inverter cancels its bubble to give a true AND. Open it in the lab and sweep all four rows._

## OR = NOR then NOT

By the exact mirror argument, a [NOR](https://digiwleea.wleeaf.dev/learn/nand-nor-build/) computes `NOT(A OR B)`, so inverting its output gives `A OR B`. A CMOS OR is a NOR followed by an inverter, again **six transistors** and **two stages**.

```
A OR B = NOT(A NOR B)
```

_Circuit diagram: OR built as a NOR feeding an inverter, mirroring the AND. Open it in the lab and confirm the output is 1 whenever either input is 1._

| A | B | NAND | AND | NOR | OR |
| --- | --- | --- | --- | --- | --- |
| 0 | 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 | 1 |

_AND is the inverse of NAND column for column; OR is the inverse of NOR. Each non-inverting gate is its inverting cousin with the output flipped, which is exactly what the extra inverter does._

> **TIP:** This has a real design consequence: skilled logic designers avoid AND and OR where they can and build directly with NAND and NOR, because it saves that extra inverter on gate after gate. The [NAND lesson](https://digiwleea.wleeaf.dev/learn/nand/) shows the systematic way to rewrite any AND-OR circuit into pure NANDs. Reach for AND and OR when clarity matters; reach for NAND and NOR when transistor count and speed matter.

> **WARN:** A tempting mistake is to imagine a "direct" AND: series NMOS to `VCC` and parallel PMOS to `GND`, or some such. It cannot work. NMOS delivers a strong `0` and belongs pulling **down**; PMOS delivers a strong `1` and belongs pulling **up**. Any arrangement that makes a single static gate non-inverting forces a transistor onto its weak side and produces degraded levels. The inversion is not a convention you can wire around; it falls out of which rail each transistor can actually reach.

**Q (Try it):** How many transistors does a 2-input AND take in static CMOS, and how many stages of delay? Compare to a 2-input NAND.

**A:** A 2-input AND takes **six** transistors (a four-transistor NAND plus a two-transistor inverter) and **two** stages of delay. A NAND is just **four** transistors and **one** stage. The AND costs 50% more transistors and twice the delay purely to cancel the natural inversion, which is why designers prefer to build with NAND and NOR directly.

### FAQ

**Q:** Why are CMOS gates naturally inverting?

**A:** Because an NMOS pull-down can only pull the output toward `0`, and it conducts for exactly the input combinations it detects. So the output is the logical inverse of the detected condition. That makes NAND, NOR, and NOT the cheap, natural gates, while a non-inverting AND or OR needs an extra inverter to cancel the inversion.

**Q:** How do you build an AND gate in CMOS?

**A:** As a NAND followed by an inverter. The NAND computes `NOT(A AND B)`; inverting it cancels the bubble and gives `A AND B`. That is six transistors (four for the NAND, two for the inverter) and two stages of delay.

**Q:** How do you build an OR gate in CMOS?

**A:** As a NOR followed by an inverter. The NOR computes `NOT(A OR B)`; inverting it gives `A OR B`. Like AND, it costs six transistors and two stages, mirroring how AND is built from NAND.

**Q:** Why do designers prefer NAND and NOR over AND and OR?

**A:** Because NAND and NOR are single-stage, four-transistor gates, while AND and OR each need an extra inverter (six transistors, two stages). Building directly with the inverting gates saves transistors and delay across a large circuit, so NAND and NOR are the practical building blocks.

> **KEY:** One gate resists this whole recipe: XOR has no compact series-parallel network. Next, after meeting the [transmission gate](https://digiwleea.wleeaf.dev/learn/transmission-gate/), we build [XOR at the transistor level](https://digiwleea.wleeaf.dev/learn/xor-transistors/).