# AND

*NAND, then inverted*

An AND gate outputs 1 only when all of its inputs are 1. In CMOS it is built as a NAND gate followed by an inverter, since a single static gate is naturally inverting.

Group: Gates
URL: https://digiwleea.wleeaf.dev/learn/and/

This is the first lesson where you place no transistors at all. You compose two parts you already made and saved: [NAND](https://digiwleea.wleeaf.dev/learn/nand/) and [NOT](https://digiwleea.wleeaf.dev/learn/not/). That jump, from wiring transistors to wiring blocks, is the same jump real chip designers make, and the one that eventually lets a handful of parts become a CPU.

**AND** produces `1` only when both inputs are `1`, and `0` otherwise. (New to the gates? The [interactive gate tour](https://digiwleea.wleeaf.dev/tools/logic-gates-explained/) lets you click the inputs of AND and every other gate and watch the output.) Beginners expect AND first, but in CMOS it is actually *more* expensive than NAND, because non-inverting behavior costs extra transistors. The practical move: build NAND (done), then invert it with NOT (done). The double inversion cancels and leaves AND.

| A | B | F |
| --- | --- | --- |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |

_Only the bottom row produces 1. Both inputs must be high._

```
F = A AND B
```

## Composing saved parts instead of adding transistors

You *could* graft two more transistors onto the NAND topology to get AND directly, but that makes a slower, larger gate. The CMOS habit is to keep building cheap inverting gates and cancel the inversion when you need a non-inverting one. Here, that means connecting the two saved parts:

1. Place your saved **NAND**. Connect `A` and `B` to its inputs. Its output is `NOT (A AND B)`: `0` only when both inputs are `1`.
2. Place your saved **NOT**. Feed the NAND output into it.
3. NOT inverts the NAND result: `NOT (NOT (A AND B))` simplifies to `A AND B`. The two inversions cancel.
4. Label the final output `F`. You now have a two-stage AND built entirely from library parts.

As an identity to confirm it: `F = NOT (A NAND B)`. NAND followed by NOT is exactly AND.

_Circuit diagram: A NAND feeding a NOT. The inversion inside NAND is cancelled by the NOT. Open it in the lab to see the two blocks wired in series._

> **WARN:** A common slip: stopping after the NAND. A NAND on its own gives `1` for the `A = B = 1` row and `0` elsewhere, the **opposite** of AND. If your "AND" reads `0` exactly where you expected `1`, you forgot the output [NOT](https://digiwleea.wleeaf.dev/learn/not/) that cancels NAND's inversion.

**Q (Try it):** Build AND as NAND -> NOT and sweep all four rows. For inputs `A = 1, B = 0`: what does the NAND output, and what does the final NOT make it?

**A:** With `A = 1, B = 0`, the NAND outputs `1` (its output is `0` only when both inputs are `1`). The NOT inverts that to `0`, the correct AND result for `1 AND 0`. Only the `A = B = 1` row makes the NAND `0`, which the NOT turns into the single `1` of AND.

> **TIP:** This is exactly how the rest of the course goes: **compose small, verified blocks into larger ones** rather than redesigning from transistors. Each level you pass saves a part, and that part is the raw material for the next.

> **KEY:** AND earns its keep soon: the **carry** of a one-bit addition is `A AND B` (next group), and a register only loads new data when a write-enable line ANDs through. You are stocking the shelf for the computer ahead.

### FAQ

**Q:** What is an AND gate?

**A:** An AND gate outputs `1` only when **all** of its inputs are `1`, and `0` otherwise. With two inputs, only the `A = B = 1` row gives `1`.

**Q:** Why is an AND gate built from a NAND and a NOT?

**A:** A single static CMOS gate is naturally inverting, so a direct AND costs extra transistors and is slower. The cheap habit is to build [NAND](https://digiwleea.wleeaf.dev/learn/nand/) (one inverting gate) and cancel its inversion with a [NOT](https://digiwleea.wleeaf.dev/learn/not/): `NOT (A NAND B) = A AND B`.

**Q:** What is the difference between AND and OR?

**A:** AND outputs `1` only when **every** input is `1` (all conditions met); [OR](https://digiwleea.wleeaf.dev/learn/or/) outputs `1` when **at least one** input is `1` (any condition met). AND is strict, OR is permissive.