# Wiring blocks into a data path

*From parts to a working circuit*

A datapath is a set of registers and an ALU joined by a shared bus, where control lines decide, each cycle, which one block drives the bus and which blocks read from it.

Group: Processor
URL: https://digiwleea.wleeaf.dev/learn/blocks-to-datapath/

> **KEY:** You now have the big blocks: an [8-bit register](https://digiwleea.wleeaf.dev/learn/register8/) that stores a byte and an [ALU](https://digiwleea.wleeaf.dev/learn/alu/) that computes on bytes. The next lesson assembles them into a [datapath](https://digiwleea.wleeaf.dev/learn/datapath/), the part of a CPU where data actually moves and is transformed. This bridge answers the question that block feels big over: given a pile of registers and an ALU, *how do they connect* without becoming a rat's nest?

The naive idea is to run a dedicated set of wires from every block to every other block. With even a few byte-wide blocks that is dozens of 8-wire bundles, and it does not scale. The insight that makes the datapath simple is the **shared bus**: instead of point-to-point wiring, all the blocks connect to one common set of wires (the bus), and they take turns using it.

## Two rules make a shared bus work

1. **Exactly one driver at a time.** Only one block may put its value onto the bus in a given cycle; every other output must let go (go to high-impedance `Z` through a tri-state buffer) so there is no contention.
2. **Any number of readers.** Blocks that need the value simply read the bus. Loading it is gated by that block's load line, so a reader captures the bus only when told to.

So a datapath is: registers and the ALU all hanging off one bus, plus **control lines** that, each cycle, raise exactly one block's "drive the bus" enable and whichever blocks' "read the bus" loads are wanted. A single operation is then "block X drives the bus, block Y loads it". Chain a few of those and you have moved and transformed data through the machine. The datapath is the *plumbing*; the control lines are the *valves*.

A concrete analogy: a single-lane loading dock shared by several warehouses. Only one truck can back into the dock at a time (one bus driver), but several crews can watch and unload what arrives (many readers). A dispatcher (the control lines) says each minute "warehouse A, load the dock; warehouses B and C, take a copy". The dock is cheap because it is shared; it works because the dispatcher enforces one loader at a time. A worked micro-cycle: to compute a sum, enable the register holding one operand onto the bus into the ALU, then enable the ALU result onto the bus and load it into a destination register.

> **WARN:** The cardinal sin of a shared bus is two drivers at once: both push a value onto the same wires and you get contention (`X` in the simulator), a garbage value and, in real hardware, wasted current. Every block that can drive the bus must do so through a [tri-state](https://digiwleea.wleeaf.dev/learn/tristate/) buffer that goes to `Z` when not selected, and the control logic must guarantee only one enable is high per cycle.

**Q (Check yourself):** In a bus-based datapath, how many blocks may drive the bus in one cycle, how many may read it, and what enforces the limit?

**A:** At most **one** block may drive the bus per cycle (more than one causes contention, `X`); **any number** may read it. The limit is enforced by the control lines, which raise exactly one driver's tri-state enable at a time while allowing several readers' load lines. Non-driving outputs sit at high-impedance `Z` so they do not fight the active driver.

### FAQ

**Q:** What is a datapath?

**A:** A datapath is the part of a processor where data is stored and transformed: registers and an ALU connected by a shared bus. Control lines decide, each cycle, which block drives the bus and which blocks read it, so data flows from one block through the ALU to another.

**Q:** Why use a shared bus instead of wiring blocks directly?

**A:** A shared bus lets many blocks exchange data over one set of wires instead of a dedicated bundle between every pair, which would not scale. The blocks take turns: one drives the bus per cycle while others read, coordinated by control lines.

**Q:** How does a bus avoid two blocks fighting over it?

**A:** Each block drives the bus through a tri-state buffer that goes to high-impedance `Z` when not selected, and the control logic raises only one drive enable per cycle. That guarantees a single driver and no contention.

> **KEY:** With the bus-and-control picture in hand, the [datapath](https://digiwleea.wleeaf.dev/learn/datapath/) lesson wires the real registers and ALU together, and after it the control unit learns to raise these lines in the right order.