# The control signal matrix

*One row per instruction, one column per lever*

A control signal matrix is a table with one row per instruction (or micro-step) and one column per control line, with a 1 wherever that line is asserted, so completing the matrix fully specifies the hardwired control unit that runs the CPU.

Group: Processor
URL: https://digiwleea.wleeaf.dev/learn/control-signals/

> **KEY:** The [control unit lesson](https://digiwleea.wleeaf.dev/learn/control/) built the matrix for one instruction, `ADD`, across its micro-steps. This page fills in the **whole** table, one row per instruction of our set, so you can see that a control unit is nothing more than a completed matrix turned into gates.

Every block in the [datapath](https://digiwleea.wleeaf.dev/learn/datapath/) has control lines: drive the bus (`*.out`), load a register (`*.load`), read or write [memory](https://digiwleea.wleeaf.dev/learn/ram/), pick the [ALU](https://digiwleea.wleeaf.dev/learn/alu/) function. The **control matrix** lists them as columns and the instructions as rows. A `1` says "this instruction raises this line"; a `0` says it leaves it low. Fill in every cell and you have specified the control unit completely.

## The shared fetch, then the execute rows

Every instruction starts with the same [fetch](https://digiwleea.wleeaf.dev/learn/fetch-cycle/): drive the program counter to memory, read the byte into the instruction register, and increment the counter. That fetch row is identical for all four instructions, so it is factored out. What differs is the **execute** phase, one row per opcode below (the operand nibble supplies the memory address where an address is needed):

| instruction (execute) | MEM.read | MEM.write | B.load | ALU.add | ACC.load | ACC.out | HALT |
| --- | --- | --- | --- | --- | --- | --- | --- |
| LOAD addr | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| ADD addr | 1 | 0 | 1 | 1 | 1 | 0 | 0 |
| STORE addr | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
| HALT | 0 | 0 | 0 | 0 | 0 | 0 | 1 |

_The execute-phase control matrix for our four-instruction set. LOAD reads memory into the accumulator; ADD also loads the ALU's B operand and adds; STORE drives the accumulator out and writes memory; HALT stops the clock. (ADD's read-then-add is really two micro-steps, folded into one row here.)_

## Reading the matrix two ways

Read **across** a row and you get everything one instruction does. Read **down** a column and you get the logic for one control line: `ACC.load` is `1` for both LOAD and ADD, so its logic is `(execute AND LOAD) OR (execute AND ADD)`, an [OR](https://digiwleea.wleeaf.dev/learn/or/) of the instructions that assert it. Each column becomes one cluster of [AND](https://digiwleea.wleeaf.dev/learn/and/)/[OR](https://digiwleea.wleeaf.dev/learn/or/) gates, and the whole set of clusters is the hardwired control unit.

> **WARN:** **Common mistakes.** The cardinal rule holds in every row: **at most one** `*.out` driver may be `1` at a time, or the shared bus shorts ([tri-state](https://digiwleea.wleeaf.dev/learn/tristate/) contention `X`). Loads (`*.load`) may overlap freely. Watch that `MEM.read` (memory drives the bus) and `MEM.write` (memory captures the bus) are never both `1` in the same step. And remember multi-step instructions like ADD occupy more than one clock even though the summary shows one row.

**Q (Try it):** Fill the execute row of the control matrix for LOAD (columns: MEM.read, MEM.write, B.load, ALU.add, ACC.load, ACC.out, HALT).

**A:** `LOAD addr` copies `memory[addr]` into the accumulator. So `MEM.read = 1` (memory drives the byte onto the bus) and `ACC.load = 1` (the accumulator captures it). Everything else is `0`: no write, no ALU operation (the value passes straight to the accumulator), no other driver, not a halt. Row: `1, 0, 0, 0, 1, 0, 0`.

### FAQ

**Q:** What is a control signal matrix?

**A:** It is a table with one row per instruction (or micro-step) and one column per control line, with a `1` wherever that instruction raises that line. Completing the matrix fully specifies a hardwired [control unit](https://digiwleea.wleeaf.dev/learn/control/): each column becomes a cluster of gates.

**Q:** How does a control matrix become hardware?

**A:** Read down each column: a control line is asserted for whichever instructions have a `1` in that column, so its logic is an [OR](https://digiwleea.wleeaf.dev/learn/or/) of those (instruction AND step) conditions. Turning every column into an AND/OR gate cluster gives the hardwired control unit.

**Q:** What is the rule about output lines in a control matrix?

**A:** In any single step at most one `*.out` line may be `1`, because two sources driving the shared bus at once is a [tri-state](https://digiwleea.wleeaf.dev/learn/tristate/) short. Load lines can overlap (many registers may sample the bus on one edge), but drivers cannot.

> **KEY:** A hardwired matrix bakes the instruction set into gates. Storing the matrix in a small memory instead makes it reprogrammable, which is [microcode](https://digiwleea.wleeaf.dev/learn/microcode/).