# Fetch, decode, execute

*The whole machine, running a program*

A CPU runs one loop forever: fetch the next instruction from memory, decode its opcode, and execute it on the datapath. Driven by the control unit and clock, those three repeating steps are a working computer.

Group: Processor
URL: https://digiwleea.wleeaf.dev/learn/cpu/

This is the summit. You have a [datapath](https://digiwleea.wleeaf.dev/learn/datapath/) (blocks on a shared bus) and a [control unit](https://digiwleea.wleeaf.dev/learn/control/) (a stepper plus decode logic). Wire the control lines to the datapath's enables, give it a clock, and the whole thing runs itself by repeating a single loop: **fetch** the next instruction, **decode** what it means, **execute** it. Round and round, one instruction per pass, for as long as the clock ticks. That loop is what makes a pile of registers and gates into a computer. Watch it run on a tiny program, step by step, in the [interactive CPU simulator](https://digiwleea.wleeaf.dev/tools/cpu-simulator/).

## The fetch-decode-execute cycle

Every instruction goes through the same three phases, sequenced by the [control unit](https://digiwleea.wleeaf.dev/learn/control/)'s ring counter.

1. **Fetch.** The [program counter](https://digiwleea.wleeaf.dev/learn/counter/) drives its address onto the bus; [RAM](https://digiwleea.wleeaf.dev/learn/ram/) reads out the instruction byte at that address; the [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/) latches it. Then the program counter increments, so it already points at the next instruction.
2. **Decode.** The [control unit](https://digiwleea.wleeaf.dev/learn/control/) looks at the instruction register's opcode and selects which sequence of control-line patterns this instruction needs. This is combinational: the opcode plus the current step picks the levers.
3. **Execute.** The control unit walks the remaining micro-steps, gating values onto the bus and loading registers, so the [datapath](https://digiwleea.wleeaf.dev/learn/datapath/) carries out the instruction: read an operand from memory, run the [ALU](https://digiwleea.wleeaf.dev/learn/alu/), store the result in the accumulator.

> **KEY:** The clock is the heartbeat. Each tick advances the [control unit](https://digiwleea.wleeaf.dev/learn/control/)'s step counter, which raises a fresh set of control lines, which causes exactly one transfer on the bus. A handful of ticks completes one instruction; then the step counter wraps, the next fetch begins, and the next instruction runs. Nothing in the machine 'decides' anything in the human sense: it is the same loop, clock after clock.

## A tiny program

Picture a four-instruction program in [RAM](https://digiwleea.wleeaf.dev/learn/ram/): load the number at address 14 into the accumulator, add the number at address 15, store the accumulator to address 13, then halt. The CPU fetches `LOAD 14`, executes it (address 14 to bus, RAM read, accumulator load). It fetches `ADD 15`, executes it (address 15 to bus, RAM read into the ALU's `B`, ALU adds, accumulator loads the sum). It fetches `STORE 13` (accumulator to bus, RAM writes address 13). It fetches `HALT` and stops the clock. You wrote arithmetic; the machine ran it. The next lesson, [tracing a program](https://digiwleea.wleeaf.dev/learn/program-trace/), follows exactly this program byte by byte, register by register.

_Circuit diagram: The execute core in action (ACCALU): driving the function code and operand over successive clocks runs a small program through the accumulator, exactly what the execute phase does once the control unit supplies those signals from a fetched instruction. The figure is shown mid-run: it has just computed clear-then-add-5, so the accumulator reads 5 (ACC0 and ACC2 high). (A full CPU adds the PC, RAM, IR, and control unit around this to fetch and decode automatically.) Open it in the lab and step a sequence, for example clear, add 5, add 10, subtract 15, and watch the accumulator compute 0, 5, 15, 0._

**Q (Check yourself):** Which of the three phases (fetch, decode, execute) is identical for *every* instruction, and which one differs depending on the opcode?

**A:** **Fetch** is identical for every instruction: drive the PC's address, read memory into the IR, increment the PC. **Decode and execute** differ by opcode: decode reads the opcode to pick which control-line pattern to use, and execute carries out that opcode's specific transfers (a LOAD reads memory into ACC, an ADD also runs the ALU, a STORE writes memory). Same fetch, opcode-specific execute.

> **TIP:** What you have built is a tiny version of a real CPU, in the spirit of the classic SAP (Simple-As-Possible) machine. Real processors pile on registers, more instructions, wider buses, pipelining, and caches, but the core loop is the same fetch-decode-execute you just traced. Speed and features grow; the idea does not.

> **KEY:** Look back at the whole climb. You started with a single [transistor](https://digiwleea.wleeaf.dev/learn/transistor/) as a switch, made [gates](https://digiwleea.wleeaf.dev/learn/nand/) from it, [arithmetic](https://digiwleea.wleeaf.dev/learn/fulladder/) and [memory](https://digiwleea.wleeaf.dev/learn/regbit/) from gates, and a [register](https://digiwleea.wleeaf.dev/learn/register8/), [ALU](https://digiwleea.wleeaf.dev/learn/alu/), [counter](https://digiwleea.wleeaf.dev/learn/counter/), [memory](https://digiwleea.wleeaf.dev/learn/ram/), and [control unit](https://digiwleea.wleeaf.dev/learn/control/) from those, and finally a machine that runs a program. Every layer was something you could open in the lab and watch work. That is a computer, built from sand up. To cement it, the final lesson [traces a real program](https://digiwleea.wleeaf.dev/learn/program-trace/) through this machine, step by step, until you can hand-execute one yourself.

### FAQ

**Q:** What is the fetch-decode-execute cycle?

**A:** It is the single loop a CPU repeats forever: **fetch** the next instruction from [memory](https://digiwleea.wleeaf.dev/learn/ram/), **decode** its opcode to see what it means, and **execute** it on the [datapath](https://digiwleea.wleeaf.dev/learn/datapath/). One instruction runs per pass, clock after clock.

**Q:** What happens during each phase of the cycle?

**A:** Fetch: the [program counter](https://digiwleea.wleeaf.dev/learn/counter/) drives an address, [RAM](https://digiwleea.wleeaf.dev/learn/ram/) reads the instruction into the [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/), and the counter increments. Decode: the [control unit](https://digiwleea.wleeaf.dev/learn/control/) reads the opcode and picks the control-line pattern. Execute: it walks the micro-steps that gate values onto the [bus](https://digiwleea.wleeaf.dev/learn/buses/) and load registers.

**Q:** Which part of the cycle is the same for every instruction?

**A:** **Fetch** is identical for every instruction: drive the PC's address, read memory into the IR, increment the PC. **Decode and execute** differ by opcode, because each opcode needs its own pattern of control lines and transfers.

**Q:** How does a CPU actually run a program?

**A:** The clock is the heartbeat: each tick advances the [control unit](https://digiwleea.wleeaf.dev/learn/control/)'s step counter, which raises a fresh set of control lines, which causes exactly one transfer on the [bus](https://digiwleea.wleeaf.dev/learn/buses/). A few ticks finish one instruction, the step counter wraps, the next fetch begins, and the next instruction runs. Nothing decides in a human sense; it is the same loop repeating.