# D flip-flop

*Master and slave*

A D flip-flop captures the value of its D input at one instant, the rising edge of the clock, and holds it until the next edge. It is built from two D latches in opposite phases (master and slave), which stops the transparency that lets glitches corrupt a plain latch.

Group: Memory
URL: https://digiwleea.wleeaf.dev/learn/dff/

The [D latch](https://digiwleea.wleeaf.dev/learn/dlatch/) fixed the forbidden-input problem but left a new one: while `EN` is high it is transparent, so noise on `D` flows straight to `Q`. A clocked computer wants to capture `D` at one precise instant, not stay open for half a cycle. The fix is to chain **two** D latches so they are never open at the same time, using a [NOT](https://digiwleea.wleeaf.dev/learn/not/) to give them opposite enables.

## Master and slave

Connect two D latches in series. The first is the **master**, the second the **slave**; the master's `Q` feeds the slave's `D`. Invert the clock into the master so the two latches see opposite enables:

```
master EN = NOT CLK
```

```
slave EN = CLK
```

When `CLK=0` the master is open and sampling `D` while the slave is closed and holding. When `CLK=1` the master closes, freezing whatever `D` was, and the slave opens and passes that frozen value to `Q`. The two open-windows never overlap, so `D` reaches `Q` only by being captured at the changeover: the **rising edge**.

## Behavior across clock edges

1. Before the first rising edge (`CLK=0`): master follows `D`, slave is closed and has never been written, so `Q` reads `Z` (undefined).
2. `CLK` rises (first edge): master closes, capturing `D` at that instant; slave opens and passes it through. `Q` takes a defined value for the first time.
3. `CLK` high, `D` changes: master is closed, so `D` does nothing; the slave's input is the frozen master value. `Q` does not move.
4. `CLK` falls: slave closes, holding `Q`; master reopens and starts tracking `D` again.
5. `CLK` rises again (second edge): master closes on the new `D`, slave passes it through, `Q` updates. This is the *only* moment `Q` can change.

> **KEY:** Edge-triggering means exactly **one moment per cycle** can change `Q`: the rising edge of `CLK`. Glitches on `D` the rest of the cycle are invisible. That predictability is why every register in every processor is built from flip-flops, not bare latches.

> **TIP:** An analogy: the [D latch](https://digiwleea.wleeaf.dev/learn/dlatch/) is a window you hold open; a flip-flop is a **camera shutter**. It takes one snapshot of `D` at the rising edge and holds that picture until the next edge, ignoring everything that happens to `D` in between. A latch watches continuously; a flip-flop samples at one instant. That instant is what makes synchronous design predictable.

_Circuit diagram: Positive-edge D flip-flop from two D latches; the NOT on CLK keeps master and slave from ever being open together. Open it in the lab and pulse CLK to watch the capture._

**Q (Try it):** Hold `D = 1` and pulse the clock once: `Q` becomes `1`. Now, with `CLK` high, change `D` to `0` (no new rising edge). Does `Q` change? When is the next moment `Q` can move?

**A:** `Q` does **not** change: the flip-flop only samples on a rising edge, and the master is closed while `CLK` is high, so changing `D` mid-cycle is ignored. The next time `Q` can move is the **next rising edge** of `CLK`, when it captures whatever `D` is at that instant. Exactly one update per cycle.

> **KEY:** This is the universal storage element of synchronous design. Your CPU's **accumulator**, its **program counter** (which flip-flop holds which instruction address), and its **instruction register** are all banks of these, every one ticking on the same clock. The next lesson gives a flip-flop the one feature a register still needs: the ability to *not* change.

> **TIP:** Probe `Q` right after power-up, before the first edge, and you will see `Z`. Expected: the master has seen `D` but the slave has not yet transferred anything out. The first rising edge initializes `Q`.

### FAQ

**Q:** What is a D flip-flop?

**A:** A D flip-flop captures the value of its `D` input at one instant, the rising edge of the clock, and holds it until the next edge. It is the standard storage element of synchronous logic.

**Q:** How is a D flip-flop built from D latches?

**A:** From two [D latches](https://digiwleea.wleeaf.dev/learn/dlatch/) in series with opposite enables (a [NOT](https://digiwleea.wleeaf.dev/learn/not/) inverts the clock into the first). The **master** samples `D` while `CLK = 0`; the **slave** passes the captured value out while `CLK = 1`. The two open windows never overlap, so `D` reaches `Q` only at the changeover edge.

**Q:** What is the difference between a D latch and a D flip-flop?

**A:** A [D latch](https://digiwleea.wleeaf.dev/learn/dlatch/) is transparent: while enabled, `Q` follows `D` continuously, so glitches pass through. A D flip-flop is edge-triggered: `Q` can change only at one instant per cycle, the rising clock edge, and ignores `D` the rest of the time.

**Q:** Why does Q read Z before the first clock edge?

**A:** On power-up the slave latch has never been written, so its output is undefined (`Z`). The master has seen `D`, but nothing has transferred through yet. The first rising edge initializes `Q` to a defined value.