# Gated D latch

*One data input, one enable*

A gated D latch stores one bit using a single Data input and an Enable input. While Enable is high the output follows D (transparent), and when Enable goes low the latch holds the last value of D. It removes the SR latch's forbidden input combination.

Group: Memory
URL: https://digiwleea.wleeaf.dev/learn/dlatch/

The [SR latch](https://digiwleea.wleeaf.dev/learn/srlatch/) can store a bit, but it makes you drive two inputs carefully and dodge the forbidden `S=R=1` state. This lesson wraps that latch in a tiny steering network built from [AND](https://digiwleea.wleeaf.dev/learn/and/) and [NOT](https://digiwleea.wleeaf.dev/learn/not/), so you control it with one **Data** line and one **Enable** line, and the forbidden state becomes impossible by construction.

## Building the steering network

Two AND gates feed the SR latch's `S` and `R` inputs:

```
S = D AND EN
```

```
R = (NOT D) AND EN
```

Because `D` and `NOT D` are always opposite, `S` and `R` can never both be `1`: the forbidden combination simply cannot occur. And when `EN=0`, both AND gates output `0` regardless of `D`, giving `S=0, R=0`, which is precisely the SR latch's hold state.

> **TIP:** That is the whole trick: `EN=0` forces `S=0, R=0`, and the latch holds automatically. No special storage circuitry is added; the [SR latch](https://digiwleea.wleeaf.dev/learn/srlatch/) you already built does the remembering.

## Transparent behavior over time

1. `EN=0`, `D` anything: `S=0, R=0`. `Q` holds its last value.
2. Raise `EN=1` with `D=1`: `S=1, R=0`, the latch sets, `Q=1`. The output followed `D`.
3. Still `EN=1`, change `D=0`: `S=0, R=1`, the latch resets, `Q=0`. `Q` followed `D` immediately.
4. Drop `EN=0`: `S=0, R=0`. `Q` holds 0 even as `D` keeps changing. The window has closed.
5. Raise `EN=1` again with `D=1`: `Q` captures the new `D` and goes to 1.
6. Drop `EN=0`: `Q` holds 1. Only `D` at the instant `EN` fell still matters.

> **WARN:** The latch is **transparent** while `EN=1`: any glitch on `D` passes straight to `Q` in real time. If `D` bounces before you lower `EN`, `Q` bounces too. That weakness is the entire reason the [D flip-flop](https://digiwleea.wleeaf.dev/learn/dff/) exists.

> **TIP:** An analogy: `EN` is a **window**. While it is open (`EN=1`) the latch watches `D` and `Q` copies it live, draughts and all. When the window shuts (`EN` drops to `0`) it freezes the last thing it saw and stops watching. Useful, but a flip-flop will want the window open for only an instant.

_Circuit diagram: Gated D latch: two AND gates steer D and NOT D into the SR core depending on EN. Open it in the lab and watch Q track D only while EN is high._

**Q (Try it):** With `EN = 1` and `D = 1`, `Q` is `1`. You drop `EN = 0`, then change `D` to `0`. What is `Q`? Then you raise `EN = 1` again. Now what is `Q`?

**A:** While `EN = 0` the latch holds, so changing `D` does nothing: `Q` stays `1`. The moment you raise `EN = 1` it becomes transparent again and immediately follows `D`, which is now `0`, so `Q` drops to `0`. The latch only captures `D` while its window is open.

> **TIP:** When you save this as a part for later levels, **pin order matters**. The simulator orders pins by position (top to bottom on each side), so place `EN` and `D` so their vertical positions match what the next level expects.

> **KEY:** The gated latch is one step from a flip-flop. Its weakness is the open window: it is transparent for as long as `EN` is high. Shrink that window to a single instant, the clock edge, and you get the rock-solid storage element of every CPU. That is the [D flip-flop](https://digiwleea.wleeaf.dev/learn/dff/), next.

### FAQ

**Q:** What is a gated D latch?

**A:** A gated D latch stores one bit using a single Data input `D` and an Enable input `EN`. While `EN` is high the output follows `D`; when `EN` goes low it holds the last value of `D`.

**Q:** How does a D latch remove the SR latch's forbidden state?

**A:** It feeds the [SR latch](https://digiwleea.wleeaf.dev/learn/srlatch/) through two AND gates: `S = D AND EN` and `R = (NOT D) AND EN`. Because `D` and `NOT D` are always opposite, `S` and `R` can never both be `1`, so the forbidden combination cannot occur.

**Q:** What does it mean that a D latch is transparent?

**A:** While `EN = 1` the output `Q` tracks `D` in real time, including any glitch on `D`. The latch is a window: open while `EN` is high, frozen when `EN` falls. That live transparency is exactly the weakness the [D flip-flop](https://digiwleea.wleeaf.dev/learn/dff/) fixes.