# Execute

*Doing what the instruction says*

Execute is the phase that raises the control lines chosen during decode so the datapath actually carries out the instruction (moving an operand, running the ALU, and loading the accumulator or writing memory), landing the result where the opcode dictates.

Group: Processor
URL: https://digiwleea.wleeaf.dev/learn/execute-cycle/

[Fetch](https://digiwleea.wleeaf.dev/learn/fetch-cycle/) retrieved the instruction and [decode](https://digiwleea.wleeaf.dev/learn/decode-cycle/) worked out what it means and which control lines it needs. **Execute** is where those lines are finally raised and the [datapath](https://digiwleea.wleeaf.dev/learn/datapath/) does the work: a byte moves across the bus, the [ALU](https://digiwleea.wleeaf.dev/learn/alu/) computes, and the result lands in the [accumulator](https://digiwleea.wleeaf.dev/learn/accumulator/) or in [memory](https://digiwleea.wleeaf.dev/learn/ram/).

## Execute differs by instruction

Unlike fetch, execute is **different for each opcode**, because each does a different thing:

- **LOAD addr:** drive `addr` to memory, read the byte onto the bus, and load it into the accumulator.
- **ADD addr:** drive `addr` to memory, send the byte to the ALU's `B` input, tell the ALU to add, and load the sum into the accumulator.
- **STORE addr:** drive the accumulator onto the bus and tell memory to write it at `addr`.
- **HALT:** stop the clock; no data moves.

Each of these is one or more micro-steps, and on each step exactly one source drives the bus while the destinations load. That is the [control unit](https://digiwleea.wleeaf.dev/learn/control/) walking the control matrix for this opcode. When execute finishes, the machine loops back to [fetch](https://digiwleea.wleeaf.dev/learn/fetch-cycle/) the next instruction.

_Circuit diagram: The execute core (ACCALU): once the control unit supplies the function code (F0, F1) and an operand (B), driving the clock carries out the operation and lands the result in ACC. Open it in the lab and step a sequence, clear, add 5, add 10, subtract 15, and watch the accumulator compute 0, 5, 15, 0. The ZERO flag lights when ACC is 0._

> **WARN:** **Common mistakes.** The cardinal rule of execute is the same as the [control matrix](https://digiwleea.wleeaf.dev/learn/control-signals/): on any one step, **at most one** source may drive the bus (two drivers is a [tri-state](https://digiwleea.wleeaf.dev/learn/tristate/) short), while any number of destinations may load. A `STORE` drives the accumulator out and lets memory read; it must not also enable another driver on that step. And execute acts on the instruction sitting in the [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/), not a fresh byte from memory, so the IR must hold steady the whole time.

**Q (Try it):** Trace which bus drivers are enabled to execute `STORE 0x3`.

**A:** `STORE 0x3` writes the accumulator to memory address 3. Execute drives the operand `0x3` as the address (from the instruction register's low nibble) and enables the **accumulator's output** onto the data bus, while raising memory's **write** line so RAM captures that byte at address 3. Exactly one data-bus driver is on (the accumulator); memory is the destination, not a second driver.

### FAQ

**Q:** What happens during the execute phase?

**A:** Execute raises the control lines chosen during [decode](https://digiwleea.wleeaf.dev/learn/decode-cycle/) so the [datapath](https://digiwleea.wleeaf.dev/learn/datapath/) actually performs the instruction: it moves an operand across the bus, runs the [ALU](https://digiwleea.wleeaf.dev/learn/alu/) if needed, and lands the result in the [accumulator](https://digiwleea.wleeaf.dev/learn/accumulator/) or writes it to [memory](https://digiwleea.wleeaf.dev/learn/ram/). Then the machine loops back to fetch.

**Q:** Why does execute differ for each instruction?

**A:** Because each opcode does something different. A LOAD reads memory into the accumulator, an ADD also runs the ALU and adds, a STORE writes the accumulator to memory, and a HALT stops the clock. The control unit raises a different pattern of control lines for each.

**Q:** What is the rule for driving the bus during execute?

**A:** At most one source may drive the shared bus on any single step; two drivers at once is a [tri-state](https://digiwleea.wleeaf.dev/learn/tristate/) short (`X`). Any number of registers may *load* from the bus on the same edge. Enforcing one driver per step is what keeps the datapath from corrupting itself.

> **KEY:** Fetch, decode, and execute together are one turn of the [CPU](https://digiwleea.wleeaf.dev/learn/cpu/)'s loop. The exact lines execute raises for each instruction are laid out in the [control signal matrix](https://digiwleea.wleeaf.dev/learn/control-signals/).