# Fetch

*Reading the next instruction from memory*

Fetch is the first phase of every instruction: the CPU reads the byte at the program counter's address out of RAM into the instruction register, then increments the program counter so it points at the following instruction.

Group: Processor
URL: https://digiwleea.wleeaf.dev/learn/fetch-cycle/

> **KEY:** The [CPU lesson](https://digiwleea.wleeaf.dev/learn/cpu/) runs the whole fetch-decode-execute loop at once. This page slows down the **first** phase, fetch, because it is the one step that is identical for every single instruction.

Fetch answers one question: **what is the next instruction?** The [program counter](https://digiwleea.wleeaf.dev/learn/program-counter/) already holds its address. So fetch drives that address to [memory](https://digiwleea.wleeaf.dev/learn/ram/), reads the instruction byte back, and parks it in the [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/) where decode can examine it. Then it bumps the program counter so the machine is ready for the instruction after this one.

1. The [program counter](https://digiwleea.wleeaf.dev/learn/program-counter/) puts its address on the bus (this is the address of the next instruction).
2. [RAM](https://digiwleea.wleeaf.dev/learn/ram/) reads out the byte stored at that address, the instruction, onto the bus.
3. The [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/) latches that byte, holding it steady for the rest of the cycle.
4. The program counter **increments** (`PC = PC + 1`), so it now points at the following instruction.

Every instruction, whether a `LOAD`, an `ADD`, a `STORE`, or a `HALT`, begins with exactly these steps. Fetch does not care what the instruction *is*; it just retrieves it. Deciding what to do with it is the next phase, [decode](https://digiwleea.wleeaf.dev/learn/decode-cycle/).

_Circuit diagram: The endpoint of fetch: the instruction register (IR8) latching a fetched byte. Set I0-I7 to an instruction byte (this stands in for RAM's output), pulse LD, and the byte is captured, its opcode on OP0-OP3 and operand on AR0-AR3 ready for decode. Before a load the outputs read Z._

> **WARN:** **Common mistakes.** The program counter increments **during fetch**, not at the end of execute, so during execute the PC already points at the *next* instruction (this matters for how jumps compute their target). On a single shared bus, fetch actually uses the bus twice (the PC drives the address, then RAM drives the byte back), so it is really two bus phases even though we describe it as one step. And the instruction register must **hold** the byte through decode and execute; if it were not latched, the changing bus would corrupt the instruction mid-cycle.

**Q (Try it):** Which registers change during fetch, and which one stays put?

**A:** The [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/) changes (it latches the fetched byte) and the [program counter](https://digiwleea.wleeaf.dev/learn/program-counter/) changes (it increments to point at the next instruction). The [accumulator](https://digiwleea.wleeaf.dev/learn/accumulator/) stays put during fetch, because fetch only retrieves the instruction; it does not do any arithmetic yet. That happens in execute.

### FAQ

**Q:** What happens during the fetch phase?

**A:** The [program counter](https://digiwleea.wleeaf.dev/learn/program-counter/) drives the address of the next instruction to [RAM](https://digiwleea.wleeaf.dev/learn/ram/), RAM reads that instruction byte onto the bus, the [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/) latches it, and the program counter increments. This retrieves the instruction and readies the machine for the one after it.

**Q:** Why is fetch the same for every instruction?

**A:** Because fetch only *retrieves* the instruction; it does not act on it. Reading a byte from the address in the program counter and latching it into the instruction register is identical whether the byte turns out to be a LOAD, an ADD, a STORE, or a HALT. The differences appear later, in [decode](https://digiwleea.wleeaf.dev/learn/decode-cycle/) and [execute](https://digiwleea.wleeaf.dev/learn/execute-cycle/).

**Q:** When does the program counter increment?

**A:** During fetch, right after the instruction is read. So by the time the instruction executes, the program counter already points at the following instruction, which is why a jump loads an absolute target address rather than adjusting the current value.

> **KEY:** With the instruction now sitting in the [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/), the next phase, [decode](https://digiwleea.wleeaf.dev/learn/decode-cycle/), splits it into an opcode and operand and works out which control lines to raise.