# Flip-flop types: D, JK, T, SR

*Four ways to clock a bit, and the tables that design them*

A flip-flop type (D, JK, T, or SR) is a one-bit edge-triggered storage cell defined by how its inputs choose the next state: D loads its input, T toggles, JK sets or resets or holds or toggles with no forbidden input, and SR sets or resets but forbids both at once. Each is described by a characteristic table (the next state as a function of the inputs and the current state) and an excitation table (the inputs needed to force a given current-to-next transition), which is the table you read when designing a sequential circuit.

Group: Memory
URL: https://digiwleea.wleeaf.dev/learn/flip-flop-types/

The [D flip-flop](https://digiwleea.wleeaf.dev/learn/dff/) captures one value at the clock edge and holds it, and the [SR latch](https://digiwleea.wleeaf.dev/learn/srlatch/) before it set or reset a bit through two control lines. Both are one-bit memory cells; they differ only in **what their inputs mean**. There are four standard flip-flop *types*, each an edge-triggered cell with a different input convention: **D**, **JK**, **T**, and **SR**. They all store exactly one bit. Choosing between them is choosing how you want to *talk* to that bit: 'load this value', 'flip it', 'set it', or 'leave it alone'.

Two small tables describe every flip-flop and let you design with it. The **characteristic table** reads the cell *forwards*: given the inputs and the current state `Q`, what is the next state `Q+` after the edge? The **excitation table** reads it *backwards*: given a transition you *want* (`Q` going to a particular `Q+`), what inputs make it happen? The forward table tells you what a cell does; the backward table is the one you actually build circuits with.

## The four characteristic tables

Write `Q+` for the next state (the value of `Q` after the clock edge) and `Q'` for NOT `Q`. Each type has a one-line **characteristic equation** that *is* its characteristic table in algebra.

**D (data): `Q+ = D`.** The simplest possible rule: the next state is whatever `D` is at the edge, regardless of the current state. Nothing to think about, and no input combination is illegal.

| Q | D | Q+ |
| --- | --- | --- |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |

_D flip-flop: Q+ = D. The current Q column does not affect the result, which is exactly why D is the easiest type to reason about._

**T (toggle): `Q+ = Q XOR T`.** With `T = 0` the bit holds; with `T = 1` it flips on every edge. Hold `T = 1` and the output changes once per clock, so its frequency is **half** the clock's. That divide-by-2 behavior is the seed of every binary [counter](https://digiwleea.wleeaf.dev/learn/counter/): chain toggling stages and each one halves the rate of the one before it.

| Q | T | Q+ |
| --- | --- | --- |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |

_T flip-flop: Q+ = Q XOR T. T = 0 holds, T = 1 toggles. The toggling case (rows 2 and 4) is the divide-by-2._

**JK: `Q+ = J·Q' + K'·Q`.** Think of `J` as a set line and `K` as a reset line, with one extra trick: when **both** are `1` the cell **toggles** instead of doing something illegal. So `JK = 00` holds, `01` resets to `0`, `10` sets to `1`, and `11` toggles. JK is the SR latch with its one forbidden corner turned into a useful operation, which made it the workhorse of the discrete-logic era.

| Q | J | K | Q+ |
| --- | --- | --- | --- |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |

_JK flip-flop: Q+ = J·Q' + K'·Q. By action: JK = 00 hold, 01 reset, 10 set, 11 toggle (the 11 rows flip Q). No input combination is forbidden._

**SR: `Q+ = S + R'·Q`, with `S·R = 0` required.** The flip-flop form of the [SR latch](https://digiwleea.wleeaf.dev/learn/srlatch/): `S` sets, `R` resets, `00` holds. Driving `S = R = 1` is still **forbidden** (it would force both outputs the same and resolve unpredictably on release), so those rows are don't-care `X` for a correct design.

| Q | S | R | Q+ |
| --- | --- | --- | --- |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | X |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | X |

_SR flip-flop: Q+ = S + R'·Q. S = R = 1 is illegal (the X rows), the one weakness JK removes by making that case a toggle._

## The excitation table: the design tool

When you *design* a sequential circuit you do not start from the inputs; you start from the **transitions you want**. A [state machine](https://digiwleea.wleeaf.dev/learn/state-machine/) or a [counter](https://digiwleea.wleeaf.dev/learn/counter/) tells you, for each storage bit, the exact `Q -> Q+` move it must make at the next edge. The **excitation table** turns that desired move into the input values that cause it. Build it once per flip-flop type and the rest of sequential design is mechanical: for every bit, look up its `Q -> Q+`, read off the inputs, and minimise that input logic with a [Karnaugh map](https://digiwleea.wleeaf.dev/learn/karnaugh/).

Reading each characteristic table backwards gives the excitation entries. The payoff is the **don't-care** cells (`X`): wherever a type can reach a transition with either value of an input, that `X` is a free choice the K-map can exploit to make the input logic smaller. The combined excitation table for all four types:

| Q | Q+ | D | T | J | K | S | R |
| --- | --- | --- | --- | --- | --- | --- | --- |
| 0 | 0 | 0 | 0 | 0 | X | 0 | X |
| 0 | 1 | 1 | 1 | 1 | X | 1 | 0 |
| 1 | 0 | 0 | 1 | X | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 | X | 0 | X | 0 |

_Excitation table: the inputs needed for each Q -> Q+ transition. D = Q+ always (trivial). T = Q XOR Q+ (toggle exactly when the bit must change). JK carries four don't-cares and SR two, which is what makes their next-state logic so easy to minimise._

## Worked example: the JK and T excitation columns

Take the four transitions one at a time and fill the JK and T entries by hand.

1. `Q: 0 -> 0` (stay low). **JK:** we must NOT set, so `J = 0`; reset or hold both keep it low, so `K` is free: `K = X`. **T:** the bit does not change, so do not toggle: `T = 0`.
2. `Q: 0 -> 1` (rise). **JK:** we must set, so `J = 1`; whether we also 'reset' is irrelevant because with `J = 1` and `K = 1` JK toggles up anyway, so `K = X`. **T:** the bit changes, so toggle: `T = 1`.
3. `Q: 1 -> 0` (fall). **JK:** we must reset, so `K = 1`; `J` is free (`J = 1, K = 1` toggles down): `J = X`. **T:** the bit changes: `T = 1`.
4. `Q: 1 -> 1` (stay high). **JK:** we must NOT reset, so `K = 0`; `J` is free (set or hold both keep it high): `J = X`. **T:** no change: `T = 0`.

Collected, that is `T = Q XOR Q+` (the single XOR you would expect from a toggle), and a JK column riddled with don't-cares: `J` only ever cares about the *rising* and *staying-high* rows, `K` only about the *falling* and *staying-low* rows. Those `X`s are exactly why a JK-based counter usually needs less gate logic than a D-based one, even though D is simpler to think about.

## Synthesising an FSM from T or JK flip-flops

So far the excitation table has just been a lookup. Now put it to work. Designing a [state machine](https://digiwleea.wleeaf.dev/learn/state-machine/) or a [counter](https://digiwleea.wleeaf.dev/learn/counter/) produces a **state table**: for every present state, the next state, which you split into one `Q -> Q+` move per storage bit. With **D** flip-flops the rest is trivial, because `D = Q+` means you wire each next-state value straight to its `D`. With **T** or **JK** you add exactly one mechanical step: run every bit's `Q -> Q+` through the excitation table to get the `T` (or the `J` and `K`) that move needs, then minimise that input with a [Karnaugh map](https://digiwleea.wleeaf.dev/learn/karnaugh/). The JK don't-cares are what keep that gate logic small.

1. Write the **state table**: for every present state list the next state, then split it into one `Q -> Q+` column per state bit.
2. Pick a flip-flop type. For each bit on each row, look its `Q -> Q+` up in the excitation table and copy in the inputs that move needs (`D`, or `T`, or `J` and `K`), writing `X` for every don't-care.
3. **K-map each flip-flop input** as a function of the present state (and any external inputs), using the `X`s as free choices to shrink the expression.
4. Wire the resulting gates into that flip-flop's input, and repeat for every bit. The flip-flops hold the state; the gates compute the next one.

**Worked example: a 2-bit up counter.** Two state bits, `Q1` (high) and `Q0` (low), stepping `00 -> 01 -> 10 -> 11 -> 00` and wrapping back to `00`. Here is its state table, with each bit's transition already visible in the next-state columns:

| Q1 | Q0 | Q1+ | Q0+ |
| --- | --- | --- | --- |
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |

_2-bit up counter, present state to next state. Q0 flips on every edge; Q1 flips only when Q0 is already 1, which is the carry out of the low bit._

Design it from **T** flip-flops first. For each bit `T = Q XOR Q+`, so set that bit's `T` to `1` on exactly the rows where the bit changes and `0` where it holds.

| Q1 | Q0 | T1 | T0 |
| --- | --- | --- | --- |
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 |

_T inputs from T = Q XOR Q+. Read the columns straight off: T0 = 1 (constant, the low bit toggles every edge) and T1 = Q0 (the high bit toggles only on a carry). No gates at all: one tie-high and one wire._

The **JK** design uses the same four rows, but each bit now takes two inputs, and the excitation table hands you a don't-care on every row:

| Q1 | Q0 | J1 | K1 | J0 | K0 |
| --- | --- | --- | --- | --- | --- |
| 0 | 0 | 0 | X | 1 | X |
| 0 | 1 | 1 | X | X | 1 |
| 1 | 0 | X | 0 | 1 | X |
| 1 | 1 | X | 1 | X | 1 |

_JK inputs from the excitation table (X = don't-care). Choosing the Xs to help: J0 = K0 = 1 (the low bit toggles) and J1 = K1 = Q0 (the high bit toggles when Q0 = 1), the same logic as the T design, because tying J = K turns a JK into a T._

Look at how the don't-cares pay off. The `J0` column reads `1, X, 1, X`; filling both `X`s with `1` collapses it to the constant `1`. The `J1` column reads `0, 1, X, X`; the two `X`s let it collapse to plain `Q0` instead of a wider expression. On a 2-bit machine each of these K-maps is only four cells you minimise by eye, but the procedure is identical at any size: one K-map per flip-flop input, drop the `X`s wherever they enlarge a group, read off the gates. That extra freedom is exactly why a JK-based (or T-based) counter historically needed fewer gates than the same machine built from D.

**Q (Try it):** Redesign the same 2-bit up counter with **D** flip-flops. Using `D = Q+`, read `D1` and `D0` straight off the transition table, then compare the gate count against the T design (`T0 = 1`, `T1 = Q0`).

**A:** `D = Q+`, so you just copy the next-state columns. `D0 = Q0+` reads `1, 0, 1, 0`, which is `Q0'` (the low bit inverts each edge). `D1 = Q1+` reads `0, 1, 1, 0`, which is `Q1 XOR Q0`. So the D version needs an inverter and a two-input XOR gate, while the T version needs only a tie-high and a single wire. Saving those gates on the toggling bits is the classic reason counters were built from T (or `J = K`) flip-flops rather than D.

_Circuit diagram: The D flip-flop, the type modern design is built around: Q+ = D, no illegal input, trivial excitation (D = Q+). Open it in the lab and pulse CLK to watch it capture D. A JK or T flip-flop is this same edge-triggered cell with a little gate logic in front that computes its D from the JK or T inputs._

> **WARN:** **Common mistakes.** Do not mix up the two tables: the **characteristic** table answers 'what does this cell do?' (forwards, inputs to `Q+`) and the **excitation** table answers 'what inputs do I need?' (backwards, a transition to inputs); design uses the excitation table. The don't-cares (`X`) in the excitation table are not errors, they are free choices you *should* feed into the K-map. Remember the JK rule for `11` is **toggle**, not 'forbidden' (that is SR), and never drive `S = R = 1` on an SR cell. Finally, a T flip-flop divides frequency by 2 only while `T` is held `1`; with `T = 0` it just holds.

**Q (Try it):** Using the excitation table, what `J` and `K` force a JK flip-flop from `Q = 1` to `Q+ = 0`? Then: what single wiring change turns a JK flip-flop into a T flip-flop, and why does it work?

**A:** For `1 -> 0` you must reset, so `K = 1`, and `J` is a don't-care (`J = X`): any `J` with `K = 1` drives it low. To make a JK behave as a T, **tie `J` and `K` together** and call that the `T` input. Then `J = K = 0` is the JK *hold* (so `T = 0` holds) and `J = K = 1` is the JK *toggle* (so `T = 1` toggles), which is precisely `Q+ = Q XOR T`. The JK is the more general cell; T and SR are special wirings of it.

> **KEY:** Why does modern design lean almost entirely on the **D** flip-flop? Because it has **no illegal input** and the **simplest possible excitation** (`D = Q+`), so a synthesis tool can target it blindly: compute the desired next-state value with combinational logic and feed it straight to `D`. JK and T shine when you are hand-minimising discrete gates (their don't-cares shrink the logic), which is why they filled the TTL catalogues, but standard-cell libraries and FPGAs standardised on D. Whichever type you pick, the excitation table is the bridge from a [state machine](https://digiwleea.wleeaf.dev/learn/state-machine/)'s desired transitions to real gates, and the next storage piece, the [register bit](https://digiwleea.wleeaf.dev/learn/regbit/), simply adds a load-enable so a D flip-flop can choose to hold.

### FAQ

**Q:** What are the four types of flip-flops?

**A:** D, JK, T, and SR. All four are one-bit edge-triggered storage cells; they differ only in what their inputs mean. **D** loads its input (`Q+ = D`), **T** toggles (`Q+ = Q XOR T`), **JK** sets, resets, holds, or toggles with no illegal input (`Q+ = J·Q' + K'·Q`), and **SR** sets or resets but forbids `S = R = 1`.

**Q:** What is the difference between a characteristic table and an excitation table?

**A:** A **characteristic** table reads a flip-flop forwards: given the inputs and the current state `Q`, it gives the next state `Q+`. An **excitation** table reads it backwards: given a desired `Q -> Q+` transition, it gives the inputs needed to cause it. You analyse with the characteristic table and *design* with the excitation table.

**Q:** What is the characteristic equation of a JK flip-flop?

**A:** `Q+ = J·Q' + K'·Q`. In words: `JK = 00` holds, `01` resets to `0`, `10` sets to `1`, and `11` toggles. The `11` toggle is what removes the SR flip-flop's forbidden `S = R = 1` state.

**Q:** Why do modern chips mostly use D flip-flops?

**A:** Because the D flip-flop has no illegal input and the simplest excitation, `D = Q+`. A synthesis tool can compute the next-state value combinationally and wire it straight to `D`, so standard-cell libraries and FPGAs standardise on it. JK and T were favoured for hand-minimised discrete logic, where their don't-care inputs shrink the gate count.

**Q:** How do you convert a JK flip-flop into a T flip-flop?

**A:** Tie `J` and `K` together and use that common line as `T`. Then `J = K = 0` is the JK hold (`T = 0` holds) and `J = K = 1` is the JK toggle (`T = 1` toggles), which is exactly the T flip-flop's `Q+ = Q XOR T`. Tying `K = J'` instead would make it behave as a D flip-flop.

**Q:** How do you use an excitation table to design a sequential circuit?

**A:** Start from the state table (for every state bit, the `Q -> Q+` move it must make at each edge). Look each move up in your chosen flip-flop's excitation table to get the inputs it needs, writing `X` for don't-cares, then K-map each flip-flop input and use the `X`s to shrink the logic. The excitation table is the bridge from the transitions you want to the gates you actually wire.

**Q:** How do you design a counter with T flip-flops?

**A:** Write the counter's state table (present state to next state), then for each state bit set that bit's `T` input to `1` on exactly the rows where the bit changes, because `T = Q XOR Q+`. K-map each `T` against the present state and read off the gates. A plain 2-bit up counter comes out as `T0 = 1` (the low bit toggles every edge) and `T1 = Q0` (the high bit toggles only on a carry from the low bit).