# Build the inverter

*Two transistors, traced row by row*

A CMOS inverter is built from one PMOS connecting the output to power and one NMOS connecting it to ground, both driven by the same input, so a 0 turns on the PMOS (output 1) and a 1 turns on the NMOS (output 0).

Group: From logic to silicon
URL: https://digiwleea.wleeaf.dev/learn/inverter-build/

Time to wire a real gate. The inverter is the smallest complementary pair, so it is the cleanest place to watch [the complementary principle](https://digiwleea.wleeaf.dev/learn/cmos-duality/) play out transistor by transistor. Its pull-down is a single NMOS and its pull-up is a single PMOS, the simplest possible dual (one transistor swapped for one transistor). This is the same gate the [NOT lesson](https://digiwleea.wleeaf.dev/learn/not/) treats as a logic function; here the focus is purely on the two transistors and the voltage on the output node.

## Place the two transistors

1. **Pull-up (PMOS)** on top: its source to `VCC`, its drain to the output node `F`, its gate to the input `A`. This is the whole pull-up network, one transistor.
2. **Pull-down (NMOS)** below: its drain to the output node `F`, its source to `GND`, its gate to the input `A`. This is the whole pull-down network, one transistor.
3. Tie the two gates together to the single input `A`, and take the output off the shared node `F` between them. That is the entire circuit: two transistors, one input, one output.

## Trace it: A = 0

Drive `A` to `0`. The PMOS gate sees `0`, so the PMOS **conducts**, connecting `F` to `VCC`. The NMOS gate also sees `0`, so the NMOS is **off**, leaving `F` disconnected from `GND`. The only live path is up to `VCC`, and the PMOS delivers a full **strong 1**. So `A = 0` gives `F = 1`.

## Trace it: A = 1

Now drive `A` to `1`. The NMOS gate sees `1`, so the NMOS **conducts**, connecting `F` to `GND`. The PMOS gate sees `1`, so the PMOS is **off**. The only live path is down to `GND`, and the NMOS delivers a full **strong 0**. So `A = 1` gives `F = 0`. In both cases exactly one transistor is on, so there is never a short and never a float, and each transistor is used on its strong side.

| A | PMOS | NMOS | F |
| --- | --- | --- | --- |
| 0 | on | off | 1 |
| 1 | off | on | 0 |

_The inverter traced. On each row exactly one transistor conducts and drives F to the opposite rail from A. That is the NOT function._

_Circuit diagram: PMOS on top to VCC, NMOS below to GND, both gates on input A, output F between them. Open it in the lab and toggle A: exactly one transistor lights up and F flips to the opposite value._

> **KEY:** Notice the pull-up is the exact dual of the pull-down here in the simplest possible way: a single series element becomes a single series element (there is nothing to swap with one transistor). Every larger gate is this same idea with more transistors in each network. Master the trace on two transistors and the four-transistor gates are just more of the same bookkeeping.

> **WARN:** The single trick that makes it an inverter is that **both** gates share the one input `A`. Wire the two gates to different signals and you no longer have a NOT: you have the start of a two-input gate. And swapping the transistors (NMOS on top, PMOS on the bottom) would put each device on its weak side and produce degraded, leaky levels, not a clean inverter. PMOS pulls up, NMOS pulls down, always.

**Q (Try it):** Build the inverter in the lab and confirm both rows. Then predict: if you accidentally tied the NMOS gate to `GND` (a permanent `0`) while the PMOS gate still follows `A`, what would the output do when `A = 1`?

**A:** With the NMOS gate stuck at `0` it is always off, so the pull-down never works. When `A = 1` the PMOS gate sees `1` and is also off, so **neither** transistor conducts and `F` floats to `Z` (not a clean `0`). This is exactly the floating-output fault the complementary design is meant to prevent, and it shows why both gates must share the real input `A`.

### FAQ

**Q:** How do you build an inverter from transistors?

**A:** Put one PMOS between the power supply and the output and one NMOS between the output and ground, and tie both gates to the same input. At input `0` the PMOS conducts and the output is `1`; at input `1` the NMOS conducts and the output is `0`. Exactly one transistor is ever on.

**Q:** Why does a CMOS inverter need both a PMOS and an NMOS?

**A:** So the output is always driven on its strong side. The PMOS pulls the output up to a full `1` when the input is `0`, and the NMOS pulls it down to a full `0` when the input is `1`. Using both, wired as a complementary pair, gives clean full-rail output with no short and no floating.

**Q:** What happens if both transistors in an inverter shared the same rail?

**A:** It would break. The inverter works because the PMOS reaches up to `VCC` and the NMOS reaches down to `GND`, so together they cover both output values. Swapping them, or wiring the gates to different signals, gives degraded levels or a floating output instead of a clean inversion.

> **KEY:** Next: add a second transistor to each network and build the two workhorse gates, [NAND and NOR](https://digiwleea.wleeaf.dev/learn/nand-nor-build/), watching the duality flip between them.