# NMOS: the strong-0 switch

*Closes on a gate 1, and pulls firmly to ground*

An NMOS transistor conducts when its gate is a 1, and it passes a strong (full-rail) 0 but only a weak 1 that stops a threshold voltage short of the supply, which is why NMOS is always used to pull an output down toward ground.

Group: From logic to silicon
URL: https://digiwleea.wleeaf.dev/learn/nmos-switch/

From [the MOSFET](https://digiwleea.wleeaf.dev/learn/mosfet/) you know an NMOS forms its channel when the gate is driven high. This lesson answers the more useful question: once it is conducting, *how well* does it pass a `0` versus a `1`? The answer is lopsided, and that lopsidedness is the single reason NMOS is used the way it is in every CMOS gate.

## When it conducts

An NMOS turns **on** when its gate is a `1` and is **off** when its gate is a `0`. Remember it as **N for eNable-on-1**. While on, its source and drain are connected and a signal can pass; while off, they are isolated. So far it is the plain switch from the last lesson.

## Strong 0, weak 1

The subtlety is what happens to the value it passes. An NMOS conducts only while its gate voltage stays at least a threshold (`Vt`) above its **source**. Watch what that means in the two cases:

1. **Passing a `0` (pulling the output down to `GND`).** The output falls toward `0 V`. As the source terminal drops, the gate (`1`, near `VCC`) stays far above it, so the gate-to-source voltage stays large and the transistor keeps conducting hard all the way down. The output reaches a clean, full-strength `0`. This is a **strong 0**.
2. **Passing a `1` (trying to pull the output up to `VCC`).** As the output rises, the source terminal rises with it. But the gate is fixed at `1` (about `VCC`), so the gate-to-source voltage keeps shrinking. The moment the output climbs to within `Vt` of the gate, the gate-to-source voltage drops to `Vt` and the channel cuts off. The output stops rising at roughly `VCC - Vt`, short of a full `1`. This is a degraded **weak 1**.

> **KEY:** An NMOS delivers a **strong 0 and a weak 1**. It is superb at dragging a wire down to ground and mediocre at pushing it up to the supply. That is why, in every static gate you will build, **NMOS is used only in the pull-down network** (the path to `GND`), never to pull an output up. Use each transistor on its strong side.

> **TIP:** An analogy: an NMOS pulling a wire high is like trying to *push* a rope up over a pulley. You can get it moving, but you lose grip near the top and it never quite reaches. Pulling the same rope *down* is easy and you can pull it all the way to the floor. The NMOS pulls down beautifully and pushes up poorly. The [PMOS](https://digiwleea.wleeaf.dev/learn/pmos-switch/) is the exact opposite.

| gate | input passed | output |
| --- | --- | --- |
| 0 | 0 | Z |
| 0 | 1 | Z |
| 1 | 0 | strong 0 |
| 1 | 1 | weak 1 |

_An NMOS used as a pass switch. Gate 0: off, nothing passes (output floats to Z). Gate 1: it passes a full-strength 0 but only a threshold-dropped weak 1._

> **WARN:** A common mistake is to reach for a lone NMOS to route a `1` somewhere (a naive pass-transistor mux, say) and then wonder why downstream gates behave oddly. That weak `1` sits below full `VCC`, so a gate reading it can leak current and switch slowly, or misread it entirely. If you must pass a full `1` through a switch, you need a [transmission gate](https://digiwleea.wleeaf.dev/learn/transmission-gate/) (an NMOS and PMOS in parallel), which restores the strong `1`.

**Q (Check yourself):** An NMOS has its gate tied to `VCC` (a permanent `1`) and you feed a `1` into one channel terminal. What does the other terminal read, and why not a full `1`?

**A:** It reads a **weak 1**, roughly `VCC - Vt`, not a full `VCC`. As the output rises it lifts the source with it, shrinking the gate-to-source voltage; once the output gets within `Vt` of the gate, the channel cuts off and it stops rising. The NMOS simply cannot deliver the top `Vt` of the range, which is exactly why it is never asked to pull an output high in a real gate.

### FAQ

**Q:** When does an NMOS transistor conduct?

**A:** An NMOS conducts when its gate is a `1` (driven high, past the threshold above its source) and is off when its gate is a `0`. Remember it as N for eNable-on-1.

**Q:** Why does an NMOS pass a strong 0 but a weak 1?

**A:** When it pulls an output down, the source stays low so the gate-to-source voltage stays large and it conducts fully, giving a strong `0`. When it tries to pass a `1`, the rising output lifts the source until the gate-to-source voltage falls to the threshold and the channel cuts off, so the output stops about a threshold voltage short of the supply: a weak `1`.

**Q:** Why is NMOS used in the pull-down network?

**A:** Because it delivers a full-strength `0` when connecting an output to ground, but only a degraded `1` when pulling up. Using it on its strong side, to pull the output down to `GND`, gives a clean logic `0`, so every static CMOS gate builds its pull-down network from NMOS.

> **KEY:** Next: the [PMOS](https://digiwleea.wleeaf.dev/learn/pmos-switch/), the mirror-image switch that closes on a `0` and delivers a strong `1`, so it takes the job of pulling outputs up.