# NOR

*NAND's mirror image*

A NOR gate outputs 1 only when both inputs are 0. It is the topological mirror of NAND, with series PMOS pulling up and parallel NMOS pulling down, and like NAND it is universal.

Group: Gates
URL: https://digiwleea.wleeaf.dev/learn/nor/

You met NOR as the worked example in [designing gates](https://digiwleea.wleeaf.dev/learn/designing-gates/); now you build it. The fastest way to understand it is as [NAND](https://digiwleea.wleeaf.dev/learn/nand/) with its two networks swapped, so keep that gate in mind as you go.

**NOR** stands for NOT-OR: the output is `1` only when both inputs are `0`. The instant either input goes `1`, the output is pulled to `0`. Like NAND, NOR is **universal**, and it has one special talent the others lack, which the [SR latch](https://digiwleea.wleeaf.dev/learn/srlatch/) will exploit to remember a bit.

| A | B | F |
| --- | --- | --- |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |

_Only the top row produces 1. Any high input drives the output low._

```
F = NOT (A OR B)
```

## The transistor network: series and parallel swapped

Place NOR next to NAND and the networks are simply exchanged. In NAND the PMOS pull-up is in **parallel** and the NMOS pull-down is in **series**. In NOR it is the opposite: PMOS in **series**, NMOS in **parallel**.

1. **Pull-up (series PMOS):** both PMOS must conduct to charge the output to `1`. A PMOS conducts on gate `0`, so both `A` and `B` must be `0`. Output is `1` only when both inputs are `0`.
2. **Pull-down (parallel NMOS):** either NMOS conducting discharges the output to `0`. An NMOS conducts on gate `1`, so if `A` or `B` is `1`, the output is pulled to `0`.
3. The two paths are complements: whenever the pull-down is off, the pull-up is on (and vice versa), so the output is always a definite `0` or `1`.

> **KEY:** **Series pull-up = AND-like at the top; parallel pull-down = OR-like at the bottom.** That is the exact swap from NAND (parallel up, series down). Once you can read those two shapes, you can read any CMOS gate at a glance.

_Circuit diagram: Two PMOS in series pulling up to VCC, two NMOS in parallel pulling down to GND. Open it in the lab and compare it side by side with your NAND._

**Q (Check yourself):** Without building it: for inputs `A = 0, B = 1`, is the NOR output `0` or `1`? Which network conducts? Then confirm against the truth table above.

**A:** `A = 0, B = 1` gives `F = 0`. The parallel NMOS pull-down conducts (the `B = 1` NMOS turns on, dragging the output to `GND`), while the series PMOS pull-up is broken because `B = 1` shuts its PMOS. Any `1` on either input pulls NOR low; only `A = B = 0` gives `1`.

## Building a whole circuit from NOR alone

Because NOR is universal, you can build an **entire** logic circuit from nothing but NOR, the same way chips build circuits from nothing but [NAND](https://digiwleea.wleeaf.dev/learn/nand/). The recipe mirrors the NAND one exactly. Take an **OR-AND** circuit, a layer of [OR](https://digiwleea.wleeaf.dev/learn/or/) gates feeding a single [AND](https://digiwleea.wleeaf.dev/learn/and/) (the product-of-sums shape you will meet in [canonical forms](https://digiwleea.wleeaf.dev/learn/canonical-forms/)), and rewrite it by **bubble pushing**:

1. Put an inversion bubble on the **output** of every first-level OR gate. An OR with an inverted output is a NOR, so each OR becomes a NOR.
2. Put a matching bubble on every **input** of the final AND gate. An AND with inverted inputs computes `A'·B' = (A + B)'`, which is a NOR by [De Morgan's law](https://digiwleea.wleeaf.dev/learn/boolean-algebra/), so the AND becomes a NOR too.
3. Each wire between the two levels now carries two bubbles back to back, and two inversions cancel, so the function never changes. Same behavior, one gate type.

```
F = (A + B)(C + D) = NOR(NOR(A, B), NOR(C, D))
```

> **TIP:** This is the exact mirror of **NAND-NAND**: an AND-OR (sum-of-products) circuit turns all-[NAND](https://digiwleea.wleeaf.dev/learn/nand/) by the same bubble-pushing move, with AND and OR swapped, just as the transistor networks are swapped. [Canonical forms](https://digiwleea.wleeaf.dev/learn/canonical-forms/) shows the full recipe for reading either one straight off a truth table.

> **TIP:** Need a plain [OR](https://digiwleea.wleeaf.dev/learn/or/)? Build NOR and cancel the inversion with the [NOT](https://digiwleea.wleeaf.dev/learn/not/) already in your library, the same trick AND used. And remember NOR for the Memory group: cross-couple two of them and you get the first circuit that can *hold* a value.

### FAQ

**Q:** What is a NOR gate?

**A:** A NOR (NOT-OR) gate outputs `1` only when both inputs are `0`. The instant either input goes `1`, the output is pulled to `0`.

**Q:** How do you build a NOR gate from transistors?

**A:** It is the [NAND](https://digiwleea.wleeaf.dev/learn/nand/) network with its two halves swapped: PMOS **in series** as the pull-up (output is `1` only when both inputs are `0`) and NMOS **in parallel** as the pull-down (any input `1` drags the output to `0`).

**Q:** Is NOR a universal gate?

**A:** Yes. Like [NAND](https://digiwleea.wleeaf.dev/learn/nand/), NOR can build every other logic gate on its own, so any digital circuit can be made from NOR gates alone.

**Q:** What is the difference between NOR and OR?

**A:** NOR is [OR](https://digiwleea.wleeaf.dev/learn/or/) with the output inverted: NOR is `1` only when both inputs are `0`, while OR is `1` whenever at least one input is `1`. NOR equals `NOT (A OR B)`.