# NOT

*The inverter*

A NOT gate, or inverter, outputs the opposite of its input: 0 becomes 1 and 1 becomes 0. It is the simplest CMOS gate, just one PMOS and one NMOS transistor working in opposition.

Group: Gates
URL: https://digiwleea.wleeaf.dev/learn/not/

This is the gate from [Complementary CMOS](https://digiwleea.wleeaf.dev/learn/cmos/), now built for real and saved as your first reusable part. It is the textbook complementary pair: one PMOS, one NMOS, the same input on both. If that lesson made sense, you already know why this works; here you wire it and keep it.

**NOT** is the inverter. Whatever you put in, you get the opposite out: feed it `0` and it returns `1`, feed it `1` and it returns `0`. It is the most fundamental gate in digital logic, and the first one you wire from raw transistors.

| A | F |
| --- | --- |
| 0 | 1 |
| 1 | 0 |

_One row per input value. The output column is always the complement._

```
F = NOT A
```

## How two transistors make an inverter

A static CMOS inverter has exactly two transistors sharing one input `A` and one output `F`. A **PMOS** sits on top, able to connect `F` to `VCC` (logic `1`). An **NMOS** sits below, able to connect `F` to `GND` (logic `0`). Both gates are tied together and driven by `A`.

1. When `A` is `0`: the PMOS gate sees `0` so it conducts; the NMOS gate sees `0` so it is off. `F` is pulled to `VCC`, giving `1`.
2. When `A` is `1`: the NMOS gate sees `1` so it conducts; the PMOS gate sees `1` so it is off. `F` is pulled to `GND`, giving `0`.
3. In every state exactly one transistor conducts, so there is never a short from `VCC` to `GND` and never a floating output.

_Circuit diagram: PMOS on top pulling to VCC, NMOS below pulling to GND, both gates sharing input A. Open it in the lab and toggle A._

**Q (Try it):** Predict the inverter's output for `A = 0`, then build it in the lab (or open the figure above) and confirm. What feeds **both** transistor gates?

**A:** `A = 0` gives `F = 1`: the PMOS conducts and pulls `F` up to `VCC`. Both transistor gates are fed by the **same** input `A`; that shared connection is what makes it an inverter. Wire them to different signals and it is no longer a NOT.

> **KEY:** The NOT gate gets **saved to your library** the moment it passes. Every later lesson that needs an inverter reaches for this part instead of re-wiring two transistors. Composing saved blocks, not redrawing transistors, is how real chip design (and the rest of this course) works.

> **TIP:** NOT shows up far beyond logic puzzles. To **subtract** in your CPU you will invert every bit of a number (the first half of two's complement), and to read a control bit's opposite you will reach for exactly this part. If you ever wire the two gates to different signals, you no longer have an inverter: the shared input is the whole trick.

### FAQ

**Q:** What is a NOT gate?

**A:** A NOT gate, or inverter, outputs the opposite of its input: `0` becomes `1` and `1` becomes `0`. It is the simplest logic gate.

**Q:** How does a CMOS inverter work?

**A:** It uses two transistors sharing one input: a PMOS on top that connects the output to `VCC` (logic `1`) and an NMOS below that connects it to `GND` (logic `0`). At input `0` the PMOS conducts and the output is `1`; at input `1` the NMOS conducts and the output is `0`. Exactly one transistor is ever on, so there is no short and no floating output.

**Q:** What is the difference between a NOT gate and a buffer?

**A:** A NOT gate inverts its input (`0` to `1`, `1` to `0`); a buffer passes the input through unchanged and just restores its strength. A buffer is two inverters in a row, since inverting twice cancels.