# OR

*NOR, then inverted*

An OR gate outputs 1 when at least one of its inputs is 1. In CMOS it is built as a NOR gate followed by an inverter, mirroring how AND is built from NAND.

Group: Gates
URL: https://digiwleea.wleeaf.dev/learn/or/

If you built [AND](https://digiwleea.wleeaf.dev/learn/and/) from NAND, you already know this lesson; just swap the parts. OR is [NOR](https://digiwleea.wleeaf.dev/learn/nor/) with a [NOT](https://digiwleea.wleeaf.dev/learn/not/) on its output, exactly as AND was NAND with a NOT. Same recipe, dual gate.

**OR** produces `1` whenever at least one input is `1`, and `0` only when both are `0`. Like AND it is non-inverting, so in CMOS you build it from its cheaper inverting cousin: NOR, then NOT.

| A | B | F |
| --- | --- | --- |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |

_Only the top row produces 0. Any high input is enough to drive the output high._

```
F = A OR B
```

## NOR then NOT: the same recipe as AND

NOR gives you `NOT (A OR B)`. Feeding that into NOT cancels the outer inversion: `NOT (NOT (A OR B))` is just `A OR B`. Two stages, two saved parts.

1. Place your saved **NOR**. Connect `A` and `B` to its inputs; its output is `NOT (A OR B)`, high only when both inputs are `0`.
2. Place your saved **NOT**. Feed the NOR output into it.
3. The result simplifies to `A OR B`.
4. Label the final output `F`. OR built from two inverting stages.

There is a second route that avoids NOR entirely: `F = (NOT A) NAND (NOT B)`. [De Morgan's law](https://digiwleea.wleeaf.dev/learn/boolean-algebra/) shows it is the same function (`NOT(A' · B') = A + B`). The NOR-then-NOT path just uses fewer parts here, because NOR is already one unit in your library.

_Circuit diagram: A NOR feeding a NOT, the dual of AND. Open it in the lab to see the pattern repeat._

**Q (Try it):** Build OR as NOR -> NOT. For inputs `A = 0, B = 0`, trace the value through the NOR and then the NOT. Why is this the only row where OR is `0`?

**A:** With `A = B = 0`, the NOR outputs `1` (NOR is high only when both inputs are `0`), and the NOT inverts it to `0`, the correct `0 OR 0 = 0`. Every other row has at least one `1`, making the NOR `0`, which the NOT turns into `1`. So only the all-`0` row gives OR a `0`.

> **KEY:** Notice the **symmetry**: AND = NAND + NOT, OR = NOR + NOT. Inverting gates are cheap in CMOS, so you build them first and cancel the inversion. That habit scales straight up to the larger blocks ahead.

> **TIP:** With OR saved you now hold all four basic gates as reusable parts (AND, OR, NAND, NOR) plus NOT. The next group spends them on arithmetic, where OR will merge the two carry signals inside a [full adder](https://digiwleea.wleeaf.dev/learn/fulladder/), the heart of your CPU's adder.

### FAQ

**Q:** What is an OR gate?

**A:** An OR gate outputs `1` when at least one of its inputs is `1`, and `0` only when every input is `0`.

**Q:** How is an OR gate built in CMOS?

**A:** As a [NOR](https://digiwleea.wleeaf.dev/learn/nor/) gate followed by a [NOT](https://digiwleea.wleeaf.dev/learn/not/), mirroring how [AND](https://digiwleea.wleeaf.dev/learn/and/) is built from [NAND](https://digiwleea.wleeaf.dev/learn/nand/): `NOT (A NOR B) = A OR B`. Inverting gates are cheaper in CMOS, so you build NOR first and cancel the inversion.

**Q:** What is the difference between OR and XOR?

**A:** They agree everywhere except when both inputs are `1`: `1 OR 1 = 1`, but `1 XOR 1 = 0`. OR is "one or the other, or both"; [XOR](https://digiwleea.wleeaf.dev/learn/xor/) is "one or the other, but not both."