# Pull-down networks

*Wiring NMOS to detect when the output should be 0*

A pull-down network is a group of NMOS transistors connecting an output to ground, arranged so it forms a conducting path (pulling the output to 0) for exactly the input combinations where the output should be 0, with series transistors giving an AND condition and parallel transistors giving an OR condition.

Group: From logic to silicon
URL: https://digiwleea.wleeaf.dev/learn/pull-down-networks/

You know from [NMOS in detail](https://digiwleea.wleeaf.dev/learn/nmos-switch/) that an NMOS pulls an output firmly to `0` and belongs in the path to ground. Now we wire several of them together into a **pull-down network**: the part of a gate that decides *when* the output gets yanked down to `GND`. This is where the switch rule from [logic as switches](https://digiwleea.wleeaf.dev/learn/logic-as-switches/), series = AND and parallel = OR, becomes a concrete recipe. (The [designing gates](https://digiwleea.wleeaf.dev/learn/designing-gates/) lesson gives the same recipe as a quick summary; here we build it up device by device.)

## What a pull-down network is

Picture the output node with a network of NMOS transistors hanging below it, and `GND` at the bottom. Each transistor's gate is driven by an input signal. For a given set of inputs, some transistors are on and some are off. If the on-transistors happen to form an unbroken path from the output all the way down to `GND`, the network **conducts** and the output is dragged to `0`. If no such path exists, the network is open and the pull-down does nothing (some other network, the pull-up, must be driving the output instead).

> **KEY:** The pull-down network **detects a condition**. It conducts, and forces the output to `0`, on exactly the input rows you wire it to. So designing a pull-down means answering one question from the truth table: *for which input combinations must the output be `0`?* Then you build a path that is complete for precisely those rows.

## Series NMOS: the AND condition

Stack two NMOS one above the other (in **series**) between the output and `GND`. Current can only reach ground if it passes through the top transistor **and** the bottom one, so **both** gates must be `1` at once for the network to conduct. A series NMOS chain conducts on the AND of its inputs: it pulls the output to `0` only when `A` **and** `B` are both `1`. Add a third in the stack and you need `A` and `B` and `C`, and so on.

_Circuit diagram: The two lower NMOS here are in series between the output and GND. The output is pulled to 0 only when both A and B are 1, the AND condition. (The parallel PMOS above form the matching pull-up, covered next lesson.) Open it in the lab and try each input row._

## Parallel NMOS: the OR condition

Now wire two NMOS side by side (in **parallel**), each on its own connecting the output to `GND`. Either transistor turning on is enough to complete a path, so the network conducts when `A` **or** `B` is `1`. A parallel NMOS pair conducts on the OR of its inputs: it pulls the output to `0` whenever at least one input is `1`. Add a third branch and any of the three being `1` pulls it down.

## Combining them: read the network off the expression

Real gates mix the two. To build a pull-down for the condition `(A AND B) OR C`, follow the structure of the expression: the product `A·B` is an AND, so `A` and `B` go in **series**; that pair is OR'd with `C`, so the whole series pair sits in **parallel** with a lone `C` transistor. Three NMOS, arranged as (`A` in series with `B`) in parallel with `C`. The path to ground completes exactly when `A·B + C` is true.

| A | B | C | pull-down conducts? |
| --- | --- | --- | --- |
| 0 | 0 | 0 | no |
| 0 | 0 | 1 | yes |
| 0 | 1 | 0 | no |
| 0 | 1 | 1 | yes |
| 1 | 0 | 0 | no |
| 1 | 0 | 1 | yes |
| 1 | 1 | 0 | yes |
| 1 | 1 | 1 | yes |

_Pull-down for (A AND B) OR C, built as (A series B) parallel C. It conducts, pulling the output to 0, on exactly the rows where A·B + C is true (every row with C = 1, plus the A = B = 1 row)._

> **WARN:** Two slips are common. First, series and parallel are about the **path to ground**, not about how the transistors happen to look on a schematic; always ask "can current get from the output to `GND` through only on-transistors?" Second, the pull-down alone does not make a working gate: on the rows where it does **not** conduct, the output would float (`Z`) unless a [pull-up network](https://digiwleea.wleeaf.dev/learn/pull-up-networks/) drives it high. A pull-down needs its complementary pull-up, which is the very next lesson.

**Q (Try it):** Design an NMOS pull-down that conducts (pulls the output to `0`) only when `A = 1`, `B = 1`, and `C = 1` all at once. Series or parallel, and how many transistors?

**A:** Three NMOS in **series** (a stack of three), gated by `A`, `B`, and `C`. Current reaches `GND` only when all three are on, i.e. all three inputs are `1`, which is the AND of all three. Any input being `0` breaks the stack and the network stops conducting. This is exactly the pull-down of a 3-input NAND.

### FAQ

**Q:** What is a pull-down network?

**A:** A pull-down network is a set of NMOS transistors wired between an output and ground so that they form a conducting path, pulling the output to `0`, for exactly the input combinations where the output should be `0`. It is one half of every static CMOS gate.

**Q:** When do NMOS transistors go in series versus parallel in a pull-down?

**A:** Series for AND, parallel for OR. Series NMOS conduct only when all their gates are `1` (the output goes `0` only when every input is `1`); parallel NMOS conduct when any gate is `1` (the output goes `0` when any input is `1`).

**Q:** How do you build a pull-down network from a Boolean expression?

**A:** Follow the expression's structure: each product term (AND) becomes NMOS in series, and terms joined by OR become parallel branches. For `(A AND B) OR C`, put `A` and `B` in series, then place that pair in parallel with a `C` transistor. The network then conducts exactly when the expression is true.

> **KEY:** Next: the [pull-up network](https://digiwleea.wleeaf.dev/learn/pull-up-networks/), the PMOS mirror that drives the output to `1` on all the other rows, built as the exact dual of the pull-down you just designed.