# Pull-up networks

*The PMOS dual that drives the output to 1*

A pull-up network is a group of PMOS transistors connecting the power supply to an output, wired as the exact dual of the pull-down network (series swapped for parallel), so it drives the output to 1 for precisely the input combinations where the pull-down does not conduct.

Group: From logic to silicon
URL: https://digiwleea.wleeaf.dev/learn/pull-up-networks/

A [pull-down network](https://digiwleea.wleeaf.dev/learn/pull-down-networks/) drags the output to `0` on the rows you choose. But on every *other* row the output would be left floating (`Z`) unless something drives it high. That something is the **pull-up network**: [PMOS](https://digiwleea.wleeaf.dev/learn/pmos-switch/) transistors between `VCC` and the output, wired so they conduct on exactly the rows the pull-down does not. Get the pairing right and the output is always driven, never floating and never shorted.

## The dual: swap series for parallel

You do not design the pull-up from scratch. You take the pull-down you already have and build its **dual**: keep each transistor gated by the same input, but turn every **series** group into a **parallel** group and every **parallel** group into a **series** group. That mechanical flip, plus the fact that a PMOS conducts on a `0` while an NMOS conducts on a `1`, guarantees the pull-up conducts on precisely the complementary set of rows.

> **KEY:** Why the dual works out: complementing a Boolean condition swaps AND with OR (that is [De Morgan's law](https://digiwleea.wleeaf.dev/learn/boolean-algebra/)), and swapping series with parallel is the physical version of swapping AND with OR. Doing both at once, the topology *and* the transistor polarity, lands you exactly on the complement. So for every input row, exactly one of the two networks conducts. That is the whole guarantee of complementary CMOS.

## Series PMOS conducts when all inputs are 0

Stack two PMOS in **series** from `VCC` to the output. Each conducts only on a gate `0`, and current must pass through both, so the network pulls the output to `1` only when `A` **and** `B` are **both** `0`. This is the pull-up of a [NOR](https://digiwleea.wleeaf.dev/learn/nor/) gate, and it is the dual of NOR's parallel NMOS pull-down (which fires when `A` **or** `B` is `1`).

_Circuit diagram: The two upper PMOS here are in series from VCC to the output: the output is pulled to 1 only when both A and B are 0. That is the dual of the parallel NMOS pull-down below it. Open it in the lab and confirm exactly one network conducts per row._

## Parallel PMOS conducts when any input is 0

Wire two PMOS in **parallel** from `VCC` to the output and either one turning on (either gate a `0`) pulls the output high. So the network conducts when `A` **or** `B` is `0`. This is the pull-up of a [NAND](https://digiwleea.wleeaf.dev/learn/nand/), the dual of NAND's series NMOS pull-down (which fires only when both inputs are `1`).

## Worked example: the dual of a compound network

Take the pull-down from the previous lesson, for the condition `(A AND B) OR C`, wired as (`A` series `B`) parallel `C`. Build its dual for the pull-up:

1. The `A` series `B` group becomes `A` **parallel** `B`.
2. That group was in parallel with `C`, so it becomes in **series** with `C`.
3. Result: (`A` parallel `B`) in series with `C`, all in PMOS, from `VCC` to the output. Three PMOS, mirroring the three NMOS below.

| A | B | C | pull-down | pull-up | output F |
| --- | --- | --- | --- | --- | --- |
| 0 | 0 | 0 | off | on | 1 |
| 0 | 0 | 1 | on | off | 0 |
| 0 | 1 | 0 | off | on | 1 |
| 0 | 1 | 1 | on | off | 0 |
| 1 | 0 | 0 | off | on | 1 |
| 1 | 0 | 1 | on | off | 0 |
| 1 | 1 | 0 | on | off | 0 |
| 1 | 1 | 1 | on | off | 0 |

_The pull-down (A series B) parallel C and its dual pull-up (A parallel B) series C. On every row exactly one conducts, so the output F = NOT(A·B + C) is always driven cleanly. This whole gate is an AND-OR-Invert._

> **WARN:** Take the dual, never re-derive the pull-up independently. If you hand-guess a PMOS network that is not the exact dual, you risk rows where **both** networks conduct (a short from `VCC` to `GND`, output `X`) or **neither** does (a floating output, `Z`). The dual construction is what mechanically rules both faults out. And note each PMOS keeps the **same** input on its gate as the NMOS it mirrors; only the series/parallel arrangement flips.

**Q (Try it):** A pull-down is three NMOS in series (a 3-input NAND's pull-down). What is the dual pull-up, and on which rows does it conduct?

**A:** The dual of three-in-series is three PMOS in **parallel**. Each PMOS conducts on a gate `0`, and any one is enough, so the pull-up conducts whenever **any** of `A`, `B`, `C` is `0`, i.e. on every row except `A = B = C = 1`. That is exactly the complement of the series pull-down (which conducts only when all three are `1`), so the gate is a 3-input NAND.

### FAQ

**Q:** What is a pull-up network?

**A:** A pull-up network is a set of PMOS transistors wired between the power supply and an output so they form a conducting path, driving the output to `1`, for exactly the input combinations where the pull-down network does not conduct. It is the other half of every static CMOS gate.

**Q:** How do you design a pull-up network from the pull-down?

**A:** Take the dual: keep each transistor gated by the same input, but swap every series group for parallel and every parallel group for series, using PMOS instead of NMOS. Because a PMOS conducts on `0` and the topology is dualized, the pull-up then conducts on exactly the rows the pull-down does not.

**Q:** Why are the pull-up and pull-down networks duals of each other?

**A:** So that for every input combination exactly one network conducts, keeping the output always driven and never shorted. Complementing a Boolean condition swaps AND with OR (De Morgan's law), and swapping series with parallel is the physical version of that, so the dual network fires on precisely the complementary rows.

> **KEY:** You can now build both halves of any gate. Next: [the complementary pair](https://digiwleea.wleeaf.dev/learn/cmos-duality/), which nails down why exactly one network is ever on and what that guarantees about the output.