# Memory: RAM *Addressable storage on a bus* RAM is a bank of registers paired with an address decoder: the address selects one cell, a write stores the data bus into it, and a read drives that cell's value back onto the bus through a tri-state. It is where a program and its data live. Group: Processor URL: https://digiwleea.wleeaf.dev/learn/ram/ Now we assemble three blocks you already have into **memory**. RAM (random-access memory) is a set of numbered storage cells: you give it an **address**, and either write the value on the data bus into that cell or read that cell's value back out. The three ingredients are storage ([registers](https://digiwleea.wleeaf.dev/learn/register8/)), addressing (a [decoder](https://digiwleea.wleeaf.dev/learn/decoder/)), and shared output ([tri-state buffers](https://digiwleea.wleeaf.dev/learn/tristate/)). ## The address picks one cell Feed the address bits into a [decoder](https://digiwleea.wleeaf.dev/learn/decoder/). It raises exactly one **select** line, the one naming the cell you want. That single select line does double duty, gating both the write into that cell and the read out of it, so only the addressed cell ever participates. ## Writing: select AND write-enable Every cell is a register sharing the common data-in bus and the clock. The trick is its write-enable: cell `k` loads only when its decoder select is high **and** a global `WR` line is high. So `WE_k = select_k AND WR`. With the address steering the decoder, a single clock edge writes the data bus into just the one addressed cell; every other cell holds. ``` WE_k = select_k AND WR (only the addressed cell loads on a write) ``` ## Reading: one tri-state onto the bus For reads, every cell's output goes onto a shared `DOUT` bus through a [tri-state buffer](https://digiwleea.wleeaf.dev/learn/tristate/), and that buffer's enable is the **same** decoder select line. Because the decoder raises only one select, only one cell drives the bus; all the others are in high-Z and stay clear. Address in, one cell's byte out, exactly the shared-bus pattern from the tri-state lesson. **Q (Try it):** In the lab: address `A1 A0 = 10`, set `DIN = 1`, raise `WR`, and clock once. Then set address `11` and read `DOUT`, then back to `10` and read again. What do you see, and why? **A:** Writing with `WR = 1` at address `10` stores `1` in cell 2 only. Reading address `11` shows `Z` (cell 3 was never written, nothing drives the bus). Reading address `10` again shows `1`: its tri-state drives the stored value back out. The decoder ensures only the addressed cell ever writes or reads. _Circuit diagram: A 4-word by 1-bit RAM (RAM4): a 2-to-4 decoder picks one of four cells; WR gates the write, and the addressed cell's tri-state drives DOUT on a read. Open it in the lab: set an address and DIN, raise WR and pulse the clock to store, then drop WR and pulse again to read it back. A cell you never wrote reads Z._ > **TIP:** This `4 x 1` memory has the entire architecture; only the numbers change for a real one. Widen each cell from one register bit to an [8-bit register](https://digiwleea.wleeaf.dev/learn/register8/) and you store a byte per address. Widen the address and decoder and you get more cells. A `16 x 8` RAM is sixteen 8-bit registers, a 4-to-16 decoder, and a byte-wide tri-state bus, wired exactly like this. > **KEY:** Memory holds both the program and its data. With the [program counter](https://digiwleea.wleeaf.dev/learn/counter/) supplying an address and RAM returning the byte there, the CPU can fetch instructions one after another. The next piece catches that fetched byte and pulls it apart into an operation and an operand: the [instruction register](https://digiwleea.wleeaf.dev/learn/instruction-register/). ### FAQ **Q:** What is RAM? **A:** RAM (random-access memory) is a bank of numbered storage cells: you give it an **address** to select one cell, then either write the value on the data bus into it or read its value back out. It is built from storage cells (each a [register](https://digiwleea.wleeaf.dev/learn/register8/)) plus a [decoder](https://digiwleea.wleeaf.dev/learn/decoder/) for addressing and [tri-state buffers](https://digiwleea.wleeaf.dev/learn/tristate/) for a shared output bus. **Q:** How does an address select a single cell in RAM? **A:** The address bits feed a [decoder](https://digiwleea.wleeaf.dev/learn/decoder/), which raises exactly one **select** line, the one naming the wanted cell. That single line does double duty: it gates the write into that cell (`WE_k = select_k AND WR`) and enables that cell's [tri-state](https://digiwleea.wleeaf.dev/learn/tristate/) onto the read bus, so only the addressed cell ever participates. **Q:** Why does reading an unwritten RAM cell give Z? **A:** On a read, only the addressed cell's [tri-state](https://digiwleea.wleeaf.dev/learn/tristate/) drives the shared `DOUT` bus; every other cell stays in high-impedance (`Z`). A cell that was never written has nothing meaningful driving it, so reading it shows `Z` rather than a defined `0` or `1`. **Q:** What is the difference between RAM and a register? **A:** A [register](https://digiwleea.wleeaf.dev/learn/register8/) is a single fixed storage location you read and write directly. RAM is *many* such cells behind an [address](https://digiwleea.wleeaf.dev/learn/decoder/): you must first select a cell by its address, then read or write it. RAM is essentially a bank of registers plus addressing and a shared bus.