# Register bit

*A flip-flop with a write enable*

A register bit is a D flip-flop plus a write-enable: when enable is high it loads new data on the clock edge, and when enable is low it feeds its own output back to hold the stored bit. It is the one-bit storage cell a register is made of.

Group: Memory
URL: https://digiwleea.wleeaf.dev/learn/regbit/

The [D flip-flop](https://digiwleea.wleeaf.dev/learn/dff/) is almost a register, but it captures `D` on *every* rising edge: you cannot tell it to leave its value alone while the rest of the circuit churns. This final Memory lesson adds a **write enable** (`WE`) and a feedback path from `Q` back to the input, so the cell loads only when you say so. It uses [AND](https://digiwleea.wleeaf.dev/learn/and/), [OR](https://digiwleea.wleeaf.dev/learn/or/), and [NOT](https://digiwleea.wleeaf.dev/learn/not/), gates you have had since the Gates group.

## The 2-to-1 selector (multiplexer)

Put a two-way selector in front of the flip-flop's `D`. It chooses between new data and the current output:

```
Din = (D AND WE) OR (Q AND NOT WE)
```

When `WE=1`, `Din = D`: the flip-flop loads the new value on the next edge. When `WE=0`, `Din = Q`: the flip-flop feeds its own output back to itself, so the next edge re-writes the value it already held. From outside, the stored bit looks frozen. This select-between-two-inputs block is a **multiplexer**, and it will reappear all over your CPU.

## Behavior over time

1. Start `WE=0, Q=0`: `Din = Q = 0`, each edge re-latches 0. `Q` holds 0.
2. Set `D=1, WE=1`: `Din = D = 1`. Next rising edge captures 1, so `Q=1`.
3. Drop `WE=0`, leave `D=1`: `Din = Q = 1`. The flip-flop keeps re-capturing 1; `Q` holds, `D` ignored.
4. Change `D=0`, `WE` still 0: `Din = Q = 1`. `Q` still holds 1, the new `D` has no effect.
5. Raise `WE=1` with `D=0`: `Din = D = 0`. Next edge captures 0, so `Q=0`.
6. Drop `WE=0`: `Q` holds 0 indefinitely.

> **TIP:** Feeding `Q` back around a flip-flop is safe *because* it only samples at the edge. Between edges `Din = Q` is stable, so the loop cannot race or oscillate; the edge just rewrites the same value. Contrast the [SR latch](https://digiwleea.wleeaf.dev/learn/srlatch/), where combinational feedback was the whole point and had to be handled with care.

_Circuit diagram: Register bit: the multiplexer on the left picks D (when WE=1) or Q (when WE=0) before the flip-flop. Open it in the lab and drive WE/D across a few clock edges._

**Q (Try it):** The cell holds `Q = 1` with `WE = 0`. You set `D = 0` but leave `WE = 0` and pulse the clock several times. What is `Q` after the pulses, and why does `D` not get in?

**A:** `Q` stays `1`. With `WE = 0` the multiplexer feeds `Din = Q`, so each edge just re-writes the value already held; the new `D` is never selected. Only raising `WE = 1` routes `D` into the flip-flop. The write enable is what makes the cell *choose* when to listen.

> **KEY:** Line up **eight** of these, share their `CLK` and `WE`, and give each its own `D` and `Q` line, and you have an **8-bit register**: it loads a byte when `WE=1` on an edge and holds otherwise. That register is the **accumulator** at the center of the CPU you are about to build, and a small bank of them is its **register file**.

> **KEY:** You now hold the complete foundation. Feedback makes state ([SR latch](https://digiwleea.wleeaf.dev/learn/srlatch/)), steering tames it ([D latch](https://digiwleea.wleeaf.dev/learn/dlatch/)), edge-triggering cleans it ([D flip-flop](https://digiwleea.wleeaf.dev/learn/dff/)), and a write enable makes it selective (this lesson). **Next: Build a CPU**, where these parts, plus the [adder](https://digiwleea.wleeaf.dev/learn/fulladder/), a multiplexer, a decoder, and a control unit, assemble into a small 8-bit computer that runs a program you write.

### FAQ

**Q:** What is a register bit?

**A:** A register bit is a [D flip-flop](https://digiwleea.wleeaf.dev/learn/dff/) plus a write-enable: when enable is high it loads new data on the clock edge, and when enable is low it feeds its own output back to hold the stored bit. It is the one-bit cell a register is made of.

**Q:** Why does a register bit need a write enable?

**A:** A bare [D flip-flop](https://digiwleea.wleeaf.dev/learn/dff/) overwrites its value on **every** clock edge, so it cannot hold a value while the rest of the circuit ticks. The write enable (`WE`) lets the cell choose when to load and when to hold.

**Q:** How does a register bit hold its value when not writing?

**A:** A multiplexer in front of the flip-flop computes `Din = (D AND WE) OR (Q AND NOT WE)`. When `WE = 0` it selects `Din = Q`, so each edge just re-writes the value already stored; the new `D` is ignored until `WE = 1`.

**Q:** How do you build an 8-bit register from register bits?

**A:** Line up eight register bits, share one `CLK` and one `WE` across all of them, and give each its own `D` and `Q` line. It loads a whole byte when `WE = 1` on an edge and holds otherwise, forming the CPU's accumulator and register file.