# An 8-bit register

*Storing a whole byte*

An 8-bit register is eight register bits sharing one clock and one write-enable, so it loads a whole byte off the bus when enabled and holds it otherwise. It is the basic storage box of a CPU.

Group: Processor
URL: https://digiwleea.wleeaf.dev/learn/register8/

The [register bit](https://digiwleea.wleeaf.dev/learn/regbit/) stores one bit: it loads `D` on a clock edge when `WE = 1`, and holds otherwise. A CPU stores whole bytes, so we need eight of those, working in lockstep. Line up eight [register bits](https://digiwleea.wleeaf.dev/learn/regbit/), tie all their clocks together and all their write-enables together, and give each its own data wire. That is an **8-bit register**, the box that holds a value on the [bus](https://digiwleea.wleeaf.dev/learn/buses/).

## Eight cells, one clock, one enable

The wiring is deliberately repetitive. Bit `i` of the input bus, `Di`, goes into register bit `i`; that cell's output is `Qi`, bit `i` of the output bus. The single `CLK` line fans out to all eight cells, and the single `WE` line fans out to all eight as well. Because every cell shares the same clock and enable, they all capture on the **same** edge, so the eight bits load as one byte, never half-and-half.

```
on a rising edge: Qi = Di if WE = 1, else Qi unchanged   (for every bit i)
```

> **KEY:** Sharing `CLK` and `WE` is the whole point. One enable controls the entire byte: assert `WE`, pulse the clock, and all eight bits update together; leave `WE` low and the stored byte is frozen no matter what the input bus does. The register has become an addressable, write-once-per-cycle storage slot.

## Load and hold over time

1. Put a byte on the input bus, say `D = 1010 0101`, and set `WE = 1`.
2. Pulse `CLK` high. On that edge every cell captures its `Di`, so `Q = 1010 0101`.
3. Drop `WE = 0`. Now change the input bus to anything you like.
4. Pulse `CLK` again. With `WE = 0` each cell re-loads its own `Q`, so the stored byte does not move. The register holds `1010 0101` until the next time you enable a write.

_Circuit diagram: An 8-bit register (REG8): eight register bits sharing CLK and WE, with an 8-bit data-in bus D0-D7 and data-out bus Q0-Q7. Before its first clock the outputs read Z (nothing stored yet), exactly like a single register bit. Open it in the lab, set a byte on D, raise WE, and run the clock to load and then hold it._

**Q (Try it):** Put the byte `0x2A` on `D`, raise `WE`, and clock once. Read `Q`. Then drop `WE = 0`, change `D` to `0xFF`, and clock several times. What does `Q` read now?

**A:** After the first clock with `WE = 1`, `Q = 0x2A` (`0010 1010`). With `WE` then held low, the register ignores `D`, so clocking does nothing: `Q` stays `0x2A` no matter that `D` is now `0xFF`. Because all eight cells share `WE`, they load or hold together, never a split byte.

> **TIP:** This one block is reused all over the machine. The **accumulator** that holds the ALU's running result is an 8-bit register. So are the **B register**, the **instruction register**, and the **program counter** (a register with an adder bolted on). A bank of several of them sharing the bus is a **register file**. Learn this box well; the CPU is mostly copies of it.

> **KEY:** A register stores a byte. The next question is what to *do* with bytes, and the first answer is arithmetic: line up eight [full adders](https://digiwleea.wleeaf.dev/learn/fulladder/) and you can add two 8-bit numbers in one shot. That is the [8-bit adder](https://digiwleea.wleeaf.dev/learn/adder8/), the core of the ALU.

### FAQ

**Q:** What is an 8-bit register?

**A:** An **8-bit register** is eight [register bits](https://digiwleea.wleeaf.dev/learn/regbit/) sharing one clock (`CLK`) and one write-enable (`WE`), so it holds a whole byte. Each bit gets its own data wire (`Di` in, `Qi` out). It is the basic storage box of a CPU.

**Q:** When does a register load versus hold?

**A:** On a rising clock edge, if `WE = 1` every cell captures its data input (`Qi = Di`); if `WE = 0` every cell re-loads its own output, so the stored byte does not change. Leave `WE` low and the value is frozen no matter what the input bus does, until you next enable a write.

**Q:** Why do all eight bits share one CLK and one WE?

**A:** So the whole byte loads as one unit, never half-and-half. The single `CLK` and single `WE` fan out to all eight cells, so they all capture on the **same** edge: assert `WE`, pulse the clock, and the eight bits update together.

**Q:** What is a register used for in a CPU?

**A:** This one block is reused all over the machine. The **accumulator** holding the ALU's running result is an 8-bit register, and so are the **B register**, the **instruction register**, and the **program counter** (a register with an [adder](https://digiwleea.wleeaf.dev/learn/adder8/) bolted on). A bank of several sharing the bus is a **register file**.