# SRAM vs DRAM

*Two ways to store a bit, and why both exist*

SRAM (static RAM) holds each bit in a six-transistor cross-coupled latch, making it fast and stable but large, while DRAM (dynamic RAM) holds each bit as charge on one capacitor guarded by one transistor, making it dense and cheap but requiring periodic refresh, which is why caches use SRAM and main memory uses DRAM.

Group: Memory
URL: https://digiwleea.wleeaf.dev/learn/sram-vs-dram/

The [RAM](https://digiwleea.wleeaf.dev/learn/ram/) you built stores each bit in a latch made of gates, which is the [register bit](https://digiwleea.wleeaf.dev/learn/regbit/) idea repeated across a grid. Real memory chips use two very different cells for that job, **SRAM** and **DRAM**, and the whole [memory hierarchy](https://digiwleea.wleeaf.dev/learn/memory-hierarchy/) exists because neither one is best at everything.

## SRAM: a bit in a latch

**Static RAM** stores each bit the way you already know: two cross-coupled inverters forming a [latch](https://digiwleea.wleeaf.dev/learn/srlatch/), plus two access transistors to read and write it. That is **six transistors per bit**. As long as power is on, the latch holds its value with no maintenance, hence *static*. It is fast (a read is just sensing a driven latch) and needs no refresh, but six transistors per bit makes it large and expensive, so you get relatively little of it.

## DRAM: a bit as charge

**Dynamic RAM** stores each bit as **charge on a tiny capacitor**, guarded by a single transistor: **one transistor and one capacitor per bit**. Charged means `1`, empty means `0`. This is far denser and cheaper per bit than SRAM, which is why main memory is DRAM. The catch: the capacitor slowly leaks, losing its charge in milliseconds, so the chip must **refresh** every cell (read it and write it back) thousands of times a second. That refreshing is why it is called *dynamic*, and it costs power and some availability.

| property | SRAM | DRAM |
| --- | --- | --- |
| cell | 6-transistor latch | 1 transistor + 1 capacitor |
| speed | fast | slower |
| density | low | high |
| cost per bit | high | low |
| refresh | none | required (periodic) |
| typical use | caches, registers | main memory |

_SRAM trades area for speed and simplicity; DRAM trades speed and refresh overhead for density and cost. Both lose their contents when power is removed (they are volatile), unlike a ROM._

> **WARN:** **Common mistakes.** Both SRAM and DRAM are **volatile**: they forget everything at power-off (do not confuse them with non-volatile flash or [ROM](https://digiwleea.wleeaf.dev/learn/rom-pla/)). "Static" does not mean permanent, it means no refresh needed while powered. And a DRAM read is **destructive** (sensing the capacitor drains it), so the chip writes the value back automatically after every read, part of why DRAM access is slower.

**Q (Try it):** Why must DRAM be refreshed but SRAM need not? Which would you use for a fast CPU cache, and why?

**A:** DRAM stores each bit as charge on a capacitor, which **leaks away** in a few milliseconds, so the value must be read and rewritten periodically (refresh) or it is lost. SRAM stores each bit in a latch that actively holds its state as long as power is on, so it never needs refreshing. A CPU cache uses **SRAM**: it must be as fast as possible and small enough to sit next to the core, and SRAM's speed and no-refresh simplicity win there even though it costs more per bit.

### FAQ

**Q:** What is the difference between SRAM and DRAM?

**A:** **SRAM** stores each bit in a six-transistor latch: fast and needs no refresh, but large and expensive, so it is used for caches and registers. **DRAM** stores each bit as charge on one capacitor with one transistor: dense and cheap, but it leaks and must be refreshed, so it is used for main memory.

**Q:** Why does DRAM need refreshing?

**A:** Each DRAM bit is charge on a tiny capacitor, and that charge leaks away within milliseconds. To keep the data, a refresh cycle reads every cell and writes it back thousands of times per second. SRAM's latch actively holds its value while powered, so it needs no refresh.

**Q:** Is SRAM or DRAM used for cache?

**A:** Cache uses **SRAM** because it must be very fast and sits right beside the CPU core. Main memory uses **DRAM** because it must be large and cheap. This speed-versus-capacity split is exactly what the [memory hierarchy](https://digiwleea.wleeaf.dev/learn/memory-hierarchy/) is built around.

> **KEY:** SRAM's speed and DRAM's density are the two ends of the [memory hierarchy](https://digiwleea.wleeaf.dev/learn/memory-hierarchy/): a small fast [cache](https://digiwleea.wleeaf.dev/learn/cache/) of SRAM in front of a large slow bank of DRAM, giving most of the speed of one and most of the capacity of the other.