# Timing: delay and the clock speed limit *Why a chip can only be clocked so fast* Propagation delay is the small time a gate takes to update its output after its inputs change. The longest delay path between clocked elements (the critical path), plus the flip-flop's setup time, sets the minimum clock period and therefore the maximum clock frequency. Group: Memory URL: https://digiwleea.wleeaf.dev/learn/timing/ > **KEY:** This lesson is about *time*, not new hardware, so it has no circuit to build. So far we have treated logic as if outputs change the instant inputs do. They do not, quite, and that small delay is what sets how fast a [clock](https://digiwleea.wleeaf.dev/learn/clock/) can run. Understanding it explains the single number everyone quotes about a CPU: its clock speed. Every gate you built is made of [transistors](https://digiwleea.wleeaf.dev/learn/transistor/) charging and discharging wires, and that takes a tiny but real amount of time. **Propagation delay** is the gap between an input changing and the gate's output settling to its new value. One gate's delay is minuscule, but signals pass through *chains* of gates, and the delays add up along the way. ## The critical path Between one bank of [flip-flops](https://digiwleea.wleeaf.dev/learn/dff/) and the next sits a cloud of [combinational](https://digiwleea.wleeaf.dev/learn/clock/) logic. A signal entering that cloud at a clock edge must travel through it and settle before the *next* edge captures the result. Different routes through the cloud take different amounts of time; the slowest one is the **critical path**. It is the critical path, not the average, that limits the clock, because the clock has to wait for the *last* bit to settle. You already saw a critical path without naming it: the [8-bit ripple-carry adder](https://digiwleea.wleeaf.dev/learn/adder8/). Its top sum bit cannot settle until the carry has rippled through all eight [full adders](https://digiwleea.wleeaf.dev/learn/fulladder/) below it, one stage at a time. That carry chain is the adder's critical path, and it is exactly why a wider ripple adder is slower: more stages, longer worst-case delay. > **TIP:** An analogy: think of the combinational logic as a **relay race** between two clock edges. The starting gun is one edge, the finish line is the next edge, and the signal is the baton passing through gates. The clock period must be long enough for the **slowest lane** (the critical path) to finish. Speed up the clock past that and the gun for the next leg fires before the baton arrives: the flip-flop captures a half-settled, wrong value. ## Setup and hold: the flip-flop's window A [flip-flop](https://digiwleea.wleeaf.dev/learn/dff/) does not capture instantaneously either. For a clean capture, its data input `D` must be steady for a short time **before** the clock edge (the **setup time**) and for a short time **after** it (the **hold time**). If `D` is still changing inside that window, the flip-flop can capture a garbled value or even hover in an undefined state. So the logic feeding a flip-flop must settle a setup-time *before* the edge, not merely by the edge. ``` minimum clock period = (critical-path delay) + (flip-flop setup time) + margin ``` Turn that period into a rate and you get the **maximum clock frequency**: the fastest the chip can be clocked and still settle correctly every cycle. A `3 GHz` processor is one whose critical path plus setup time fits inside one-three-billionth of a second. Make the critical path shorter (for example a [carry-lookahead adder](https://digiwleea.wleeaf.dev/learn/adder8/) instead of ripple) and you can clock faster, computing the *same* answers in less time. > **WARN:** A faster clock never makes a result *more correct*, and pushing past the limit makes it *wrong*: the flip-flops latch values the logic had not finished computing. This is the real danger the [clock](https://digiwleea.wleeaf.dev/learn/clock/) lesson warned about, made precise. It is also why overclocking has a ceiling, and why the headline fix for speed is shortening the critical path (better logic, [pipelining](https://digiwleea.wleeaf.dev/learn/cpu/)), not just turning the clock up. **Q (Check yourself):** Two combinational paths run between the same pair of flip-flops: one takes 3 ns to settle, the other 7 ns. Ignoring setup time, what is the shortest clock period that still works, and which path decided it? **A:** The shortest safe period is **7 ns**, set by the **slower** (7 ns) path, the **critical path**. The clock must wait for the last signal to settle, so the slowest route through the logic sets the limit even though the other path finished in 3 ns. (Add the flip-flop's setup time and a safety margin for the real minimum.) > **KEY:** Timing is the bridge between the *logical* circuit (does it compute the right function?) and the *physical* one (how fast can it run?). Everything in this course is logically correct at any clock speed; timing is what decides the speed. With storage, the clock, and its limits understood, you are ready to assemble these blocks into the [processor](https://digiwleea.wleeaf.dev/learn/buses/), where one shared clock drives the whole machine. ### FAQ **Q:** What is propagation delay? **A:** Propagation delay is the short time a [gate](https://digiwleea.wleeaf.dev/learn/nand/) takes to update its output after its inputs change, because its [transistors](https://digiwleea.wleeaf.dev/learn/transistor/) must charge and discharge real wires. One gate's delay is tiny, but signals pass through chains of gates, so the delays add up along each path. **Q:** What is the critical path in a digital circuit? **A:** The critical path is the slowest delay route through the [combinational](https://digiwleea.wleeaf.dev/learn/clock/) logic between two banks of [flip-flops](https://digiwleea.wleeaf.dev/learn/dff/). It sets the clock limit because the clock must wait for the *last* signal to settle, not the average. The [ripple-carry adder](https://digiwleea.wleeaf.dev/learn/adder8/)'s carry chain is a classic critical path. **Q:** What are setup and hold time? **A:** Setup time is how long a [flip-flop](https://digiwleea.wleeaf.dev/learn/dff/)'s data input must be steady **before** the clock edge; hold time is how long it must stay steady **after**. If the data is still changing inside that window, the flip-flop can capture a wrong or undefined value, so the feeding logic must settle a setup-time before the edge. **Q:** What sets a CPU's maximum clock speed? **A:** The minimum clock period is the critical-path delay plus the flip-flop setup time (plus a margin), and the maximum frequency is one divided by that period. A `3 GHz` chip fits its critical path plus setup time into one-three-billionth of a second. Clock faster than that and flip-flops latch values the logic had not finished computing.