# Verilog: the other HDL

*Describing hardware in a C-like language*

Verilog is a hardware description language (HDL) that, like VHDL, describes digital hardware as text so it can be simulated and synthesised into real gates; its unit of design is the module (a named block with an input/output port list), and its C-like syntax makes it the most common HDL in US chip design.

Group: HDL
URL: https://digiwleea.wleeaf.dev/learn/verilog-intro/

You met [VHDL](https://digiwleea.wleeaf.dev/learn/vhdl-intro/), one way to describe hardware as text. **Verilog** is the other. Both are IEEE-standard HDLs that a synthesis tool turns into the same gates you build on the canvas; the difference is dialect. VHDL reads like Ada: verbose, strongly typed, strict. Verilog reads like C: terse, case-sensitive, quick to write. Most US universities and most commercial chip (ASIC) design lean Verilog; European and defense work leans VHDL. Learn to read both and no HDL codebase is foreign.

## The module: Verilog's building block

Where VHDL splits a design into an **entity** (the interface) and an **architecture** (the guts), Verilog folds both into one **module**. A module has a name, a **port list** (its inputs and outputs, the pins), and a body that describes the logic. `module ... endmodule` wraps the whole thing, just as `entity`/`architecture` did. A port is `input`, `output`, or `inout` (bidirectional, for a shared bus). Here is a two-input AND gate:

```verilog
module and_gate(
  input  A,
  input  B,
  output F
);
  assign F = A & B;
endmodule
```

_A Verilog module for an AND gate. The port list names the pins (two inputs, one output); the single assign line is the logic. Compare it to the VHDL entity/architecture: same circuit, fewer words._

Read it as the diagram it is: a box named `and_gate` with pins `A`, `B`, and `F`, and inside, one AND gate (`&`) driving `F` from `A` and `B`. The port list is the box's boundary, the [INPUT and PROBE](https://digiwleea.wleeaf.dev/learn/vhdl-entity/) markers you place on the canvas; the `assign` line is the wire-and-gate inside. That is the whole idea: a module is a labelled circuit block.

> **WARN:** Two Verilog habits that trip up VHDL users: Verilog is **case-sensitive**, so `clk` and `CLK` are different names, and every statement ends with a **semicolon** `;`. Comments are C-style: `//` to end of line, or `/* ... */`. Miss a semicolon or mismatch a name's case and the tool complains, so stay consistent from the start.

> **KEY:** Why this matters: Verilog and VHDL describe the *same* hardware, so everything you learned building circuits, gates, adders, registers, a CPU, maps to both. The next two lessons show the two core styles in Verilog: `assign` for [combinational logic](https://digiwleea.wleeaf.dev/learn/verilog-combinational/) (a standing gate network) and `always @(posedge clk)` for [sequential logic](https://digiwleea.wleeaf.dev/learn/verilog-sequential/) (memory), the exact pair you met as concurrent assignments and processes in VHDL.

**Q (Try it):** In the AND-gate module, which line is the *interface* (the box's pins) and which is the *logic* (what is inside)? And what would you change to make it a two-input OR gate?

**A:** The port list `input A, input B, output F` is the interface, the pins on the box. The line `assign F = A & B;` is the logic inside. To make it OR, change the operator `&` (AND) to `|` (OR): `assign F = A | B;`. The interface stays the same; only the gate inside changes, exactly like swapping the part on your canvas while keeping its I/O.

### FAQ

**Q:** What is Verilog?

**A:** Verilog is a hardware description language (HDL): a text language for describing digital circuits so they can be simulated and synthesised into real gates. It has a C-like syntax and is the most widely used HDL in US chip (ASIC) design.

**Q:** What is the difference between Verilog and VHDL?

**A:** Both are IEEE-standard HDLs that synthesise to the same hardware. Verilog is terser and C-like (case-sensitive, semicolons), popular in US industry and ASIC design; VHDL is more verbose and strongly typed (Ada-like), popular in Europe and defense work. Learning one makes the other easy to read.

**Q:** What is a module in Verilog?

**A:** A module is Verilog's basic design block: a named unit with a port list (its input/output pins) and a body describing the logic, all wrapped in module ... endmodule. It is the equivalent of a VHDL entity plus architecture combined, and it corresponds to one labelled circuit block.

**Q:** Is Verilog case-sensitive?

**A:** Yes. In Verilog, clk and CLK are two different names, unlike VHDL which is case-insensitive. Every statement also ends in a semicolon, and comments use C-style // or /* */.