# XOR at the transistor level

*The gate with no simple series-parallel network*

XOR outputs 1 exactly when its two inputs differ, and because it has no compact single-stage static CMOS network it is built either from several NAND gates or, more compactly, from transmission gates that pass A when B is 0 and NOT A when B is 1.

Group: From logic to silicon
URL: https://digiwleea.wleeaf.dev/learn/xor-transistors/

Every gate so far dropped straight out of the series = AND, parallel = OR recipe. **XOR** is the exception, and it is worth seeing why. XOR outputs `1` exactly when its two inputs **differ**: `A XOR B = A'·B + A·B'`. That expression has no arrangement of a few series and parallel transistors that computes it in one inverting stage, because it needs *both* an input and its complement in the pull-down. So XOR is always built out of other pieces. Two ways are standard.

| A | B | F |
| --- | --- | --- |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |

_XOR: 1 exactly when the inputs differ. Notice it flips whenever either single input changes, which is what defeats a simple pull-down network._

## Way 1: from gates (the NAND build)

Because [NAND is universal](https://digiwleea.wleeaf.dev/learn/nand/), XOR can be assembled from NAND gates alone. The classic arrangement uses **four** 2-input NANDs and computes `A XOR B` without a separate inverter. This is the build the [XOR lesson](https://digiwleea.wleeaf.dev/learn/xor/) walks through, and it is how the sum bit of an adder is usually made. It is robust and fully restoring (every stage is a real driven gate), at the cost of several gates of delay.

_Circuit diagram: XOR assembled from NAND gates. Each stage is a fully driven CMOS gate, so the output is clean and restored. Open it in the lab and confirm the output is 1 only when the inputs differ._

## Way 2: from transmission gates (the compact build)

There is a slicker view. Look at XOR one input at a time: when `B = 0`, `A XOR B = A`; when `B = 1`, `A XOR B = NOT A`. In other words, **XOR is a selector**: use `B` to choose between passing `A` and passing `A'`. That is exactly a 2-to-1 multiplexer, which [transmission gates](https://digiwleea.wleeaf.dev/learn/transmission-gate/) build cheaply.

1. Make `A'` with one inverter (2 transistors) and `B'` with one inverter (2 transistors). The `B` and `B'` pair are the complementary controls for the transmission gates.
2. Transmission gate 1 passes `A` to the output when `B = 0` (its NMOS gated by `B'`, its PMOS by `B`).
3. Transmission gate 2 passes `A'` to the output when `B = 1` (its NMOS gated by `B`, its PMOS by `B'`).
4. Exactly one transmission gate is enabled at a time, so the output is `A` when `B = 0` and `A'` when `B = 1`: that is `A XOR B`, in roughly eight transistors.

Trace it against the truth table: `A=0,B=0` selects `A` = `0`; `A=1,B=0` selects `A` = `1`; `A=0,B=1` selects `A'` = `1`; `A=1,B=1` selects `A'` = `0`. Every row matches. Flip the roles (pass `B` and `B'` selected by `A`) and you get the same function, since XOR is symmetric.

> **KEY:** XNOR (the complement of XOR, `1` when the inputs are equal) comes for free from the same idea: just swap which input the transmission gates pass, sending `A'` when `B = 0` and `A` when `B = 1`, or simply invert the XOR output. XOR and its sibling XNOR are the reason a pure series-parallel mindset is not quite enough; selection and pass logic round out the toolkit.

> **WARN:** The transmission-gate XOR is compact but **not restoring**: its output is a passed signal, not one freshly driven from the rails, so it sags a little and slows if you feed it straight into a long chain of more pass logic. Designs that use it usually follow it with an inverter or buffer to clean the level back up. If you need a rock-solid, high-fan-out XOR, the fully driven NAND build is the safer choice. And do not try to widen XOR into a single 3-input gate: a multi-input XOR is a **parity** function and is always built as a chain of 2-input XORs.

**Q (Try it):** Explain, using "XOR is a selector," why `A XOR B` equals `A` when `B = 0` and `NOT A` when `B = 1`. Then say how many transistors the transmission-gate build uses.

**A:** XOR is `1` when the inputs differ. Hold `B = 0`: the output is `1` exactly when `A` differs from `0`, i.e. when `A = 1`, so the output just follows `A`. Hold `B = 1`: the output is `1` when `A` differs from `1`, i.e. when `A = 0`, so the output is `NOT A`. That is a mux selecting `A` or `A'` by `B`. The build uses two inverters (for `A'` and `B'`, four transistors) plus two transmission gates (four transistors), about eight transistors total.

### FAQ

**Q:** Why can't XOR be built as a single simple CMOS gate?

**A:** Because `A XOR B = A'·B + A·B'` needs both an input and its complement in the pull-down network, and its output flips whenever either input changes. No small series-parallel arrangement of transistors captures that in one inverting stage, so XOR is built from other gates or from transmission gates plus inverters.

**Q:** How do you build an XOR gate from transistors?

**A:** Two common ways. From gates: use four 2-input NAND gates, which is fully restoring but several stages deep. From pass logic: use two transmission gates as a 2-to-1 multiplexer that passes `A` when `B` is `0` and `NOT A` when `B` is `1`, which is about eight transistors but does not restore the signal.

**Q:** Why is XOR the same as a 2-to-1 multiplexer selected by one input?

**A:** Because `A XOR B` equals `A` when `B` is `0` and `NOT A` when `B` is `1`. So `B` selects between passing `A` and passing its complement, which is exactly a 2-to-1 multiplexer choosing between `A` and `A'`.

**Q:** How do you build an XNOR gate from transistors?

**A:** XNOR is the complement of XOR (it is `1` when the inputs are equal). Either invert an XOR's output, or swap which value the transmission gates pass so the mux sends `A'` when `B` is `0` and `A` when `B` is `1`.

> **KEY:** You have now built every basic gate from transistors. Next: [transistor count and sizing](https://digiwleea.wleeaf.dev/learn/transistor-sizing/), the practical intuition for how many transistors a gate really costs and how big to make them.