# XOR

*The odd one out*

An XOR (exclusive-OR) gate outputs 1 exactly when its two inputs differ. No single static CMOS gate computes it, so it is built from a small network of NAND gates, and it forms the core of binary addition.

Group: Gates
URL: https://digiwleea.wleeaf.dev/learn/xor/

This lesson leans entirely on [NAND](https://digiwleea.wleeaf.dev/learn/nand/) and its universality. XOR has no direct transistor recipe like the gates before it, so instead of running the [design method](https://digiwleea.wleeaf.dev/learn/designing-gates/) you will *compose* four NANDs. It is your first taste of building a function that no single gate provides, which is most of what real logic design is.

**XOR** (exclusive OR) produces `1` when its two inputs are **different**, and `0` when they are the same. Another way to say it: the output is `1` exactly when an odd number of inputs are `1` (a parity check). Unlike AND, OR, NAND, and NOR, there is no single CMOS transistor pair that does XOR, so you combine simpler gates.

| A | B | F |
| --- | --- | --- |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |

_Output is 1 in the two rows where the inputs differ. The last row, both 1, gives 0, which is what distinguishes XOR from OR._

```
F = A XOR B
```

## Building XOR from four NAND gates

The classic four-NAND construction shares one intermediate signal `M = A NAND B`, then combines it with each input. Walk the truth-table rows after each step to convince yourself it holds.

1. Compute `M = A NAND B` with one NAND. `M` is `0` only when both inputs are `1`; otherwise `1`.
2. Compute `P = A NAND M` with a second NAND. When `A` is `0`, `P` is `1`. When `A` is `1` and `M` is `1` (so `B` is `0`), `P` is `0`. When `A` is `1` and `M` is `0` (both inputs `1`), `P` is `1`.
3. Compute `Q = B NAND M` with a third NAND. Symmetric to `P`, using `B` instead of `A`.
4. Compute `F = P NAND Q` with the fourth NAND. Check: when the inputs differ, one of `P`/`Q` is `0`, so `F` is `1`. When both are `0`, both `P` and `Q` are `1`, so `F` is `0`. When both are `1`, `M` is `0`, so again `P` and `Q` are `1` and `F` is `0`.

An alternative uses your saved parts directly: `F = (A OR B) AND (A NAND B)`, which reads naturally as "at least one input is `1`, but not both." This simulator's level builds the four-NAND version, because it shows off NAND's universality.

_Circuit diagram: Four NANDs: one computes M, two combine each input with M, and a final NAND produces the output. Open it in the lab and toggle the inputs through all four rows._

> **WARN:** Do not confuse XOR with [OR](https://digiwleea.wleeaf.dev/learn/or/). They agree on three rows and differ on the last: `1 XOR 1 = 0` but `1 OR 1 = 1`. XOR is "one or the other, **but not both**"; OR is "one or the other, **or both**." That single row is the whole difference, and it is what makes XOR the sum bit of an adder while OR is not.

**Q (Try it):** Use XOR as a controllable inverter. If one XOR input is a control line `C` and the other is data `D`, what comes out when `C = 0`? When `C = 1`?

**A:** `D XOR 0 = D` (passes through unchanged), and `D XOR 1 = NOT D` (inverted). So `C` decides whether `D` passes straight through or flipped. This is exactly the trick the adder uses to [subtract](https://digiwleea.wleeaf.dev/learn/subtract/): flip every bit of one operand on command.

> **KEY:** **XOR is the heart of binary addition.** Adding two single bits, the sum bit is `A XOR B` and the carry bit is `A AND B`. The [half adder](https://digiwleea.wleeaf.dev/learn/halfadder/) in the next group is literally those two gates side by side, and a row of them becomes the adder in your CPU's ALU. Everything in the Arithmetic group follows from this gate.

> **TIP:** Because XOR detects when two signals differ, it also drives comparators, parity/error checks, and (flip its inputs) controllable inverters: feeding one XOR input a control line turns the other input through or inverted on command. That trick is exactly how your CPU's adder will subtract.

**Spot the fault** (Wrong logic level): A=1, B=1, F=1. Look at F.

For `A = 1, B = 1` a correct XOR outputs `0`, since the inputs are the same, but this gate reads `1`. It is computing OR, not XOR. The two functions agree on every row except this one: `1 XOR 1 = 0` while `1 OR 1 = 1`.

### FAQ

**Q:** What is an XOR gate?

**A:** An XOR (exclusive-OR) gate outputs `1` exactly when its two inputs **differ**, and `0` when they are the same. Equivalently, it outputs `1` when an odd number of inputs are `1` (a parity check).

**Q:** Why does XOR need multiple gates instead of one transistor pair?

**A:** No single static CMOS gate computes XOR, so it is built from a small network of simpler gates. A classic construction uses four [NAND](https://digiwleea.wleeaf.dev/learn/nand/) gates: one makes `M = A NAND B`, two combine each input with `M`, and a fourth produces the output.

**Q:** What is the difference between XOR and OR?

**A:** They match on three input rows and differ on the last: `1 XOR 1 = 0` but `1 OR 1 = 1`. XOR means "one or the other, but not both"; [OR](https://digiwleea.wleeaf.dev/learn/or/) means "one or the other, or both." That single row is what makes XOR the sum bit of an adder.

**Q:** Why is XOR important for binary addition?

**A:** Adding two single bits, the sum bit is `A XOR B` and the carry bit is `A AND B`. So the [half adder](https://digiwleea.wleeaf.dev/learn/halfadder/) is just an XOR and an AND, and a row of those becomes the adder in a CPU's [ALU](https://digiwleea.wleeaf.dev/learn/alu/).