OR gate using NAND gates: three gates, live

An OR gate takes three NAND gates: two NANDs with their inputs tied together invert A and B, and a third NANDs the inverted inputs, so Y = NAND(NOT A, NOT B) = A OR B. Try all four input rows on the live circuit below.

The reason is De Morgan's law: NOT (NOT A AND NOT B) = A OR B. A NAND gate computes exactly the left side when it is fed the inverted inputs, and a NAND with both inputs joined is an inverter (NAND(A, A) = NOT A). So OR from NAND gates is "invert both inputs, then NAND". In a schematic the same idea shows up as a NAND gate drawn with bubbles on its inputs, which is an OR. With NAND gates OR costs three gates while XOR costs four; the universal gates page builds NOT, AND, OR and NOR from NANDs side by side, and the AND gate from three NOR gates is the mirror image of this circuit.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

Embed or cite this circuit

Free to embed on a course page, blog or worksheet: paste this code. The circuit stays live, and the small digiwleea badge links back here.

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To cite it: digiwleea, “OR gate from NAND gates”, https://digiwleea.wleeaf.dev/tools/build/or-from-nand/

What you need

2× NAND: inverters, each with both inputs tied: NOT A and NOT B
1× NAND: Y = NAND(NOT A, NOT B) = A OR B

Step by step

Place inputs A and B and a probe Y.
Feed A into both inputs of a NAND gate: its output is NOT A. Do the same for B.
NAND the two inverted signals together and probe the result as Y.
Try all four rows: Y is 0 only when A and B are both 0, which is OR.

OR from NAND truth table

A	B	NOT A	NOT B	Y = A OR B
0	0	1	1	0
0	1	1	0	1
1	0	0	1	1
1	1	0	0	1

The last NAND outputs 0 only when both of its inputs are 1, that is when A and B are both 0. All four rows are checked on the live circuit before the page is built.

You can also read the full theory in the lesson on the NAND gate. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

More builds: Universal gates: NAND only, NOR only

AND gate from NAND gates NOR gate from NAND gates NOT gate from a NOR gate OR gate from NOR gates NOT gate from a NAND gate AND gate from NOR gates XNOR gate from NAND gates XOR gate from NOR gates XOR gate from NAND gates XNOR gate from NOR gates CNOT gate half adder from NAND gates

All 246 build guides, by topic

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the OR gate from NAND gates in the lab →

Frequently asked

How many NAND gates are needed to make an OR gate?

Three: two NAND gates used as inverters (inputs tied together) and one NAND that combines the inverted inputs. NAND(NOT A, NOT B) = A OR B by De Morgan's law.

How do you make a NOT gate from a NAND gate?

Connect both inputs of the NAND gate together. NAND(A, A) = NOT (A AND A) = NOT A.

How do you make an AND gate from NAND gates?

Use two: a NAND followed by a NAND wired as an inverter. NOT (NAND(A, B)) = A AND B.

How many NAND gates make a NOR gate?

Four: the three-NAND OR gate followed by one more NAND wired as an inverter.