Skip to content
digiwleeaTools
LearnGlossaryAboutCheat sheetHow a CPU worksToolsOpen the lab →

How to build a half adder using only NAND gates

A half adder can be built from five NAND gates and nothing else: four of them form the XOR that gives the sum S = A XOR B, and the fifth inverts the shared NAND(A, B) to give the carry C = A AND B.

NAND is a universal gate, so any circuit can be made from NANDs alone, and the half adder is the classic exercise. The trick that keeps it at five gates is sharing: the first NAND, NAND(A, B), is both the first stage of the 4-NAND XOR and, inverted, the carry. Compare it with the ordinary half adder from an XOR and an AND: same truth table, one gate type.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

Step by step

  1. Place inputs A and B and feed both into a first NAND gate, N1.
  2. Build two more NANDs: one with inputs A and N1, one with inputs B and N1.
  3. NAND the outputs of those two gates together. The result is A XOR B; probe it as the sum S.
  4. For the carry, feed N1 into both inputs of a fifth NAND. A NAND with its inputs tied together is a NOT, so it outputs NOT NAND(A, B) = A AND B. Probe it as C.
  5. Toggle A and B through 00, 01, 10, 11 and check the sum and carry against the truth table below.

Half adder truth table

ABSC
0000
0110
1010
1101

Identical to the half adder built from XOR and AND, because it is the same function. In the lab you can go one level further: every NAND gate here is itself four CMOS transistors, so the whole half adder is 20 transistors.

You can also read the full theory in the lesson on the half adder. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adderfull adderhalf subtractorfull subtractor2:1 multiplexer4:1 multiplexerXOR gate from NAND gates2-to-4 decoderSR latchD flip-flopJK flip-flopT flip-flop4-bit shift register4-bit ripple carry adderD latch1-to-4 demultiplexer4-bit magnitude comparator4-bit ring counter4-bit Johnson counter4-to-2 priority encoder4-bit synchronous counter3-to-8 decoder8-to-1 multiplexer4-bit carry lookahead adder2-bit comparator

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the half adder from NAND gates in the lab →

Frequently asked

How many NAND gates are needed for a half adder?

Five. Four NAND gates make the XOR for the sum, and the first of those, NAND(A, B), is reused: a fifth NAND with both inputs tied to it inverts it into A AND B for the carry.

Why can a half adder be built from NAND gates only?

NAND is functionally complete: NOT, AND and OR can all be made from NANDs, so any Boolean function can be. A NAND with its inputs tied is a NOT, a NAND followed by that NOT is an AND, and XOR takes four NANDs.

How many NAND gates does a full adder need?

Nine is the usual minimum: two NAND-only half adders share their first gates, and the final OR of the carries becomes one NAND because the carries arrive already inverted.

How do you make a half adder from NOR gates?

The same idea works with NOR, which is also universal, but the gate counts differ: an XOR takes five NOR gates (or four for XNOR plus one inverter), and the carry A AND B is NOR(NOT A, NOT B).