How to build a 4:1 multiplexer from logic gates

A 4:1 multiplexer picks one of four inputs to pass through using two select lines, and is built from two NOT gates, four AND gates (one per input), and an OR gate that merges them.

A 4-to-1 mux is the next size up from the 2:1 mux: four data inputs D0..D3, two select lines S1 S0, and one output Y. The two select bits form a 2-bit address that names which input reaches the output. In the live circuit each AND is fed three signals and the final OR four, which the lab builds from the two-input gates you already have.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× NOT — the inverted select lines, NOT S1 and NOT S0
4× AND — one per data input, each gated by the matching select combination
1× OR — merging the four gated paths into Y

Step by step

Place six inputs: the four data lines D0, D1, D2, D3, and the two select lines S1 and S0.
Invert each select line with a NOT gate, giving NOT S1 and NOT S0.
AND D0 with NOT S1 and NOT S0: this path is live only for select 00. Do the same for D1 with NOT S1 and S0 (01), D2 with S1 and NOT S0 (10), and D3 with S1 and S0 (11).
OR the four AND outputs together into Y. Because exactly one select combination is ever true, only one path is active and Y follows the chosen input.
Probe Y and step the select lines through 00, 01, 10, 11 to watch each data input take its turn at the output.

4:1 multiplexer select table

S1	S0	Y
0	0	D0
0	1	D1
1	0	D2
1	1	D3

The two select bits are a 2-bit address choosing which input reaches Y. The full truth table has 64 rows (six inputs), but this compact form captures the whole behaviour: Y equals the data input named by S1 S0. Cascade three 2:1 muxes and you get the same 4:1 mux; scale the pattern and a mux routes data all through a processor.

You can also read the full theory in the lesson on multiplexers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder half subtractor full subtractor 2:1 multiplexer XOR gate from NAND gates 2-to-4 decoder SR latch D flip-flop JK flip-flop

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab and course.

Open the 4:1 multiplexer in the lab →

Frequently asked

What gates build a 4-to-1 multiplexer?

Two NOT gates for the inverted select lines, four AND gates (one per data input, each combined with the matching select combination), and one OR gate to merge them. Its logic is Y = D0 S1' S0' + D1 S1' S0 + D2 S1 S0' + D3 S1 S0.

How many select lines does a 4-to-1 multiplexer need?

Two. The number of select lines is the base-2 log of the number of inputs, so 4 inputs need 2 select bits, 8 inputs need 3, and 16 inputs need 4. The select bits form the address of the chosen input.

How do you build a 4:1 mux from 2:1 muxes?

Use three 2:1 muxes: two first-stage muxes select between D0/D1 and D2/D3 using S0, and a third mux picks between those two results using S1. That tree gives the same behaviour as the single-gate 4:1 design.

Can a 4-to-1 multiplexer implement a logic function?

Yes. Wiring the two variables to the select lines and driving each data input with 0, 1, or a third variable lets a 4:1 mux realize any 3-variable Boolean function, which is why multiplexers are called universal logic elements and are the basis of FPGA lookup tables.