How to build a SR latch from logic gates

An SR latch stores one bit and is built from just two cross-coupled NOR gates, each gate's output feeding back into the other's input.

This is the first circuit that remembers. Two NOR gates wired output-to-input form a feedback loop that holds its state after the inputs go away. Set (S) forces the stored bit to 1; Reset (R) forces it to 0; with both low, it holds.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× NOR — cross-coupled to form the storage loop

Step by step

Place two inputs, S (set) and R (reset), and two NOR gates.
Feed R into the first NOR gate; its output is Q, the stored bit.
Feed S into the second NOR gate; its output is Q̄ (Q-bar), the opposite of Q.
Cross-couple them: wire Q̄ back into the first NOR's other input, and Q back into the second NOR's other input. This feedback is what holds the value.
Pulse S = 1 and Q latches to 1; release it and Q stays 1. Pulse R = 1 and Q drops to 0 and stays. Holding both at 0 keeps whatever was stored.

SR latch behaviour

S	R	Q (next)
0	0	hold
1	0	1
0	1	0
1	1	avoid

With both inputs low the latch holds its last value: that is the memory. Asserting both S and R at once is the forbidden case (it forces both outputs low and the next state is ambiguous). Add an enable and a data line and this latch becomes a D latch, then a flip-flop.

You can also read the full theory in the lesson on the SR latch. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder 2:1 multiplexer D flip-flop

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab and course.

Open the SR latch in the lab →

Frequently asked

What gates make an SR latch?

The classic SR latch is two cross-coupled NOR gates: each gate's output is wired back to an input of the other. (You can also build one from two cross-coupled NAND gates, which gives an active-low SR latch.)

How does an SR latch store a bit?

The two NOR gates feed back into each other, so once an output settles high or low the loop reinforces it. That self-reinforcing feedback holds the bit even after S and R return to 0.

Why should S and R not both be 1 at the same time?

Asserting both forces both outputs to 0, which breaks the Q and Q-bar complement relationship, and when the inputs release together the final state is unpredictable. Well-behaved designs never drive both high at once.