How to build a 2:1 multiplexer from logic gates

A 2:1 multiplexer picks one of two inputs to pass through based on a select line, and is built from one NOT gate, two AND gates, and one OR gate.

A multiplexer (mux) is a data selector: a switch you control with logic. The select line S chooses whether input A or input B reaches the output Y. It is one of the most reused building blocks in a CPU.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

1× NOT — inverting the select line
2× AND — gating each input with the (inverted) select
1× OR — merging the two gated paths into Y

Step by step

Place three inputs: the two data inputs A and B, and the select line S.
Invert the select with a NOT gate, giving NOT S.
AND input A with NOT S: this path is live only when the select is 0.
AND input B with S: this path is live only when the select is 1.
OR the two AND outputs together into the output Y. Because only one path is ever active, Y follows A when S is 0 and B when S is 1.

2:1 multiplexer truth table

S	A	B	Y
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	0
1	0	1	1
1	1	0	0
1	1	1	1

When S = 0 the output Y equals A; when S = 1 it equals B. Stack these to build wider muxes: a 4:1 mux is three 2:1 muxes, and muxes route data all through a processor.

You can also read the full theory in the lesson on multiplexers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder SR latch D flip-flop

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab and course.

Open the 2:1 multiplexer in the lab →

Frequently asked

What gates build a 2:1 multiplexer?

A 2:1 mux takes one NOT gate, two AND gates, and one OR gate. Its logic is Y = (A AND NOT S) OR (B AND S).

What is the boolean expression for a 2:1 mux?

Y = (A AND NOT S) OR (B AND S). The select S enables one AND path at a time, and the OR merges them, so Y is A when S is 0 and B when S is 1.

Can you build a multiplexer with only NAND gates?

Yes. NAND is universal, so the NOT, AND and OR in a mux can each be built from NAND gates, giving an all-NAND 2:1 multiplexer.