How to build a D flip-flop from logic gates

A D flip-flop captures its data input on the clock's rising edge and is built from two gated D latches in series (a master and a slave) with the clock inverted between them.

A plain latch is transparent: while it is enabled the output tracks the input. A flip-flop is stricter: it only samples on the clock edge, which is what makes synchronous design predictable. The trick is two latches, each itself made of gates, run on opposite clock phases so their open windows never overlap.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× D latch — master samples, slave holds (each is AND/NOT gates around an SR latch)
1× NOT — inverting the clock so master and slave are never open together

Step by step

Place a clock CLK and a data input D.
Invert the clock with a NOT gate. The inverted clock enables the first (master) latch; the raw clock enables the second (slave) latch.
Feed D into the master D latch. While CLK = 0 the master is open and follows D; the slave is closed and holding.
Wire the master's output into the slave D latch. When CLK rises to 1 the master freezes whatever D was at that instant, and the slave opens and passes that frozen value to the output Q.
Because the two latches are never open at the same moment, D reaches Q only at the rising edge. Probe Q and pulse the clock to watch it capture exactly once per cycle.

D flip-flop behaviour

CLK	D	Q (next)
rise	0	0
rise	1	1
0 or 1 (steady)	x	hold
fall	x	hold

The only moment Q can change is the rising edge, when it takes the value of D. Any change to D between edges is ignored. That one-update-per-cycle predictability is why every register in a processor is built from flip-flops, not bare latches.

You can also read the full theory in the lesson on the D flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder 2:1 multiplexer SR latch

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab and course.

Open the D flip-flop in the lab →

Frequently asked

What gates make a D flip-flop?

A positive-edge D flip-flop is two gated D latches in series (a master and a slave) plus one NOT gate on the clock. Each D latch is itself built from AND and NOT gates around an SR latch, so the whole thing reduces to logic gates.

What is the difference between a D latch and a D flip-flop?

A D latch is level-sensitive: while enabled its output follows D continuously. A D flip-flop is edge-triggered: it samples D only at the clock edge and holds the rest of the cycle. The flip-flop is two latches on opposite clock phases.

Why does a D flip-flop need two latches?

One latch would be transparent while enabled, letting data ripple straight through. Putting a master and a slave on opposite clock phases means only one is ever open, so data advances by exactly one stage per clock edge instead of racing through.