Glossary

Every term in the course, defined in one line and linked to its lesson. Jump to a letter, or scan A to Z.

A

The accumulator: The accumulator is the single working register at the center of an accumulator-machine CPU: arithmetic and logic operations implicitly use it as one operand and write their result back into it, so an instruction like ADD means add a memory value to the accumulator.
Adding 8-bit numbers: A ripple-carry adder chains eight full adders, each carry-out feeding the next adder's carry-in, so it adds two 8-bit numbers in a single pass. It is the arithmetic core the ALU is built around.
Addressing modes: An addressing mode is the rule a CPU uses to find an instruction's operand: immediate keeps the value inside the instruction, direct (absolute) keeps the operand's memory address in the instruction, indirect keeps the address of the address, and indexed adds a base and an offset to compute the address.
Algorithmic state machines (ASM charts): An algorithmic state machine (ASM) chart is a flowchart-style notation for a finite state machine, built from three boxes (a rectangular state box that names a state and lists its Moore outputs, a diamond decision box that tests one input and branches, and a rounded conditional-output box that asserts a Mealy output only on a chosen path), where one ASM block (a state box plus the decision and conditional-output boxes below it) is everything that happens in a single clock cycle.
The ALU: An ALU (arithmetic logic unit) performs one of several operations on two input bytes, selected by a function code, and reports status such as a zero flag. It bundles the adder/subtractor with bitwise logic behind a multiplexer to form the CPU's compute unit.
always @(posedge clk): A clocked always @(posedge clk) block in Verilog describes edge-triggered sequential logic, and assigning a reg with the nonblocking operator <= inside it captures a value on the rising clock edge, synthesising to a D flip-flop or register.
Analyzing a sequential circuit: Analyzing a sequential circuit is the reverse of designing one: starting from an unknown clocked netlist of flip-flops and gates, you read each flip-flop's input equations off the gates, substitute them into the flip-flop's characteristic equation to get every next-state bit, tabulate the result as a state table, draw the state diagram, and read off in words what the machine does.
AND: An AND gate outputs 1 only when all of its inputs are 1. In CMOS it is built as a NAND gate followed by an inverter, since a single static gate is naturally inverting.
AND and OR: the price of not inverting: Because every static CMOS gate is naturally inverting, AND is built as a NAND followed by an inverter and OR as a NOR followed by an inverter, so each non-inverting gate costs six transistors and two stages of delay instead of a NAND or NOR's four transistors and one stage.
ASCII and character encoding: ASCII is a character encoding that assigns every letter, digit, punctuation mark, and control code a 7-bit number from 0 to 127, so text is stored as a sequence of byte codes: 'A' is 65 (0x41), '0' is 48 (0x30), and 'a' is 97 (0x61).
Assembly language: Assembly language is a human-readable form of machine code in which each instruction is written as a short mnemonic (such as LOAD or ADD) that an assembler translates one-to-one into the opcode byte the CPU executes.

B

The barrel shifter: A barrel shifter is a combinational circuit that shifts or rotates a word by any amount in a single step, built from a tree of multiplexer stages where stage k shifts by 0 or 2^k under one control bit; a logical shift fills the vacated bits with 0, an arithmetic right shift copies the sign bit, and a rotate wraps the bits around.
Binary division: Binary division computes a quotient and a remainder by shift-and-subtract, the hardware form of long division: for each bit from the top, shift the running remainder, try to subtract the divisor, and if it fits set that quotient bit to 1 and keep the subtraction, otherwise set it to 0 and restore.
Binary multiplication: A hardware multiplier forms a binary product by ANDing the multiplicand with each bit of the multiplier to make shifted partial products, then adding those partial products together; multiplying two n-bit numbers gives a result of up to 2n bits.
Binary numbers: Binary is the base-2 number system: every value is written with just two digits, 0 and 1, so it maps directly onto a wire that is off or on. Each column is worth twice the column to its right.
Binary-coded decimal (BCD): Binary-coded decimal (BCD) stores each decimal digit in its own 4-bit group using the 8421 weights, so the digits 0 to 9 map to 0000 to 1001 and the six patterns 1010 to 1111 are unused.
A bit is a number and a truth value: A bit is both a binary digit and a truth value: the same `0` and `1` that spell a number in binary also stand for false and true, so the algebra of logic and the digits of arithmetic operate on the exact same wires.
Bits, bytes, and KiB vs KB: A byte is 8 bits, and larger amounts of storage use prefixes that come in two flavors: binary prefixes (KiB, MiB, GiB) that multiply by 1024, and decimal SI prefixes (KB, MB, GB) that multiply by 1000, which is why a drive's advertised size looks smaller once formatted.
Boolean algebra: Boolean algebra is the mathematics of true and false: variables take only the values 0 or 1, combined with AND, OR, and NOT. Its identities and De Morgan's laws let you rewrite a logic expression into the simpler circuit that computes the same function.
Boolean identities and duality: Boolean identities are the fixed laws (identity, null, idempotent, complement, and absorption) that hold for any inputs, and the duality principle says swapping every AND with OR and every 0 with 1 in a true identity yields another true identity, so together they let you simplify a logic expression by hand.
Build NAND and NOR: A CMOS NAND is built from two series NMOS pulling down and two parallel PMOS pulling up (output 0 only when both inputs are 1), and a CMOS NOR is its exact mirror with two parallel NMOS and two series PMOS (output 1 only when both inputs are 0); each uses four transistors.
Build the inverter: A CMOS inverter is built from one PMOS connecting the output to power and one NMOS connecting it to ground, both driven by the same input, so a 0 turns on the PMOS (output 1) and a 1 turns on the NMOS (output 0).
The build, name, reuse ladder: Abstraction in digital design is the repeated move of building a thing from smaller things, verifying it against its specification, giving it a name, and reusing it as one sealed block, from transistor to gate to adder to CPU.
Buses: A bus is a group of wires, one per bit, routed together so they carry a whole multi-bit number at once. It is the plumbing and notation that lets the parts of a CPU pass bytes between each other.

C

Caches and the memory hierarchy: A cache is a small, fast memory that holds recently and nearby-used data so the processor can avoid the slow trip to main memory, and the memory hierarchy is the stack of register, cache, DRAM, and disk levels that keeps the data most likely to be needed in the fastest level that can hold it.
Canonical forms: minterms and maxterms: Canonical forms are the two standard ways to write a logic function straight from its truth table: the sum of minterms (a canonical SOP, one AND term per 1-row, all ORed) and the product of maxterms (a canonical POS, one OR term per 0-row, all ANDed), each of which maps directly onto a two-level gate circuit.
Carry versus overflow: Carry-out signals that an unsigned addition result did not fit in the available bits, while overflow signals that a signed two's-complement result did not fit, so the identical adder output is judged by the carry flag when the numbers are unsigned and by the overflow flag when they are signed.
Carry-lookahead adders: A carry-lookahead adder speeds up addition by computing all of the carries in parallel directly from the input bits, using per-bit generate and propagate terms, instead of waiting for each carry to ripple up one bit at a time.
The clock and sequential logic: A clock is a signal that switches steadily between 0 and 1 to pace a circuit, and sequential logic is logic whose outputs depend on stored state, not just the present inputs. The clock tells every memory element exactly when to update so the whole circuit changes in lockstep.
Comparators: A comparator is a combinational circuit that reports whether one binary number is greater than, equal to, or less than another, built from per-bit equality (XNOR) and greater/less logic that resolves from the most significant bit downward.
Complementary CMOS: Complementary CMOS builds a logic gate from a PMOS pull-up network to power and a complementary NMOS pull-down network to ground, with exactly one network conducting for any input so the output is always driven cleanly to 0 or 1.
The complementary pair: A complementary CMOS gate joins a PMOS pull-up network and its dual NMOS pull-down network at a shared output, so that for every input combination exactly one network conducts, driving the output to a full-rail 0 or 1 with no floating and no short.
Concurrent assignments: A concurrent signal assignment in VHDL (signal <= boolean expression) describes a piece of combinational logic that is always active, the same standing gate network the expression denotes, and it can be derived directly from a truth table as a sum of products.
The consensus theorem: The consensus theorem states that `A·B + A'·C + B·C` equals `A·B + A'·C`: the consensus term `B·C` is logically redundant and can be dropped, and re-adding it is precisely the extra gate used to remove a static-1 hazard.
Continuous assignment: A continuous assignment in Verilog (assign wire = expression) describes a piece of combinational logic that is always active, the same standing gate network the expression denotes, and it can be derived directly from a truth table as a sum of products using & for AND, | for OR, and ~ for NOT.
The control signal matrix: A control signal matrix is a table with one row per instruction (or micro-step) and one column per control line, with a 1 wherever that line is asserted, so completing the matrix fully specifies the hardwired control unit that runs the CPU.
The control unit: The control unit is the sequencer that steps through the micro-operations of each instruction, raising the control lines that gate values onto the bus and trigger register loads. A ring counter supplies the steps, and the current opcode selects which lines fire on each one.

D

D flip-flop: A D flip-flop captures the value of its D input at one instant, the rising edge of the clock, and holds it until the next edge. It is built from two D latches in opposite phases (master and slave), which stops the transparency that lets glitches corrupt a plain latch.
The datapath: The datapath is every storage and compute block wired onto one shared bus, each gated on by a control line, so data flows from a source, optionally through the ALU, into a destination, one transfer per clock step.
De Morgan's laws: De Morgan's laws say the inverse of an AND is an OR of the inverses and the inverse of an OR is an AND of the inverses, so `NOT (A AND B) = (NOT A) OR (NOT B)` and `NOT (A OR B) = (NOT A) AND (NOT B)`, which is how you push a NOT through a gate and convert between NAND and NOR forms.
Decode: Decode is the phase that splits the fetched instruction into its opcode (which operation) and operand (its data), then uses the opcode to select which control lines the execute phase must raise.
Decoders: A decoder turns an n-bit binary address into one-hot outputs, raising exactly the single output named by the address. It is how an address selects one specific register or memory location.
Designing a sequence detector: A sequence detector is a finite state machine that watches a serial input and raises its output when a target bit pattern arrives; you design one by writing a state diagram, filling a state-transition and output table, assigning a binary code to each state, and reading the next-state and output equations off the table, choosing a Moore output (from the state alone) or a Mealy output (from the state and the current input).
Designing gates from truth tables: You can derive any static CMOS gate from its truth table: build an NMOS pull-down network that conducts for exactly the rows where the output is 0, then mirror it with a complementary PMOS pull-up. Series transistors create AND conditions, parallel transistors create OR conditions.

E

Encoders and demultiplexers: An encoder turns a one-hot set of input lines into the binary address of the active line, the reverse of a decoder. A demultiplexer routes one data input to one of several outputs chosen by a select code, the reverse of a multiplexer.
Entity and architecture: In VHDL, the entity declares a circuit's external interface (its named input and output ports), and the architecture describes the implementation inside that interface; together they fully specify one design block.
Error detection and correction: Error-detecting and error-correcting codes add redundant bits to data so that bit flips can be caught (parity) or even located and repaired (Hamming codes), at the cost of extra storage or bandwidth.
Execute: Execute is the phase that raises the control lines chosen during decode so the datapath actually carries out the instruction (moving an operand, running the ALU, and loading the accumulator or writing memory), landing the result where the opcode dictates.

F

Fetch: Fetch is the first phase of every instruction: the CPU reads the byte at the program counter's address out of RAM into the instruction register, then increments the program counter so it points at the following instruction.
Fetch, decode, execute: A CPU runs one loop forever: fetch the next instruction from memory, decode its opcode, and execute it on the datapath. Driven by the control unit and clock, those three repeating steps are a working computer.
Finite state machines: A finite state machine (FSM) is a circuit that holds one of a fixed set of states in a register and, on each clock edge, moves to a next state chosen by combinational logic from the current state and inputs. It is the standard way to build a controller that steps through a sequence.
Fixed-point fractions: Fixed-point is a way to represent fractions by placing an imaginary binary point at a fixed bit position, so bits left of the point carry the usual positive powers of two and bits right of it carry negative powers (1/2, 1/4, 1/8), letting ordinary integer hardware handle fractional values.
Flip-flop types: D, JK, T, SR: A flip-flop type (D, JK, T, or SR) is a one-bit edge-triggered storage cell defined by how its inputs choose the next state: D loads its input, T toggles, JK sets or resets or holds or toggles with no forbidden input, and SR sets or resets but forbids both at once. Each is described by a characteristic table (the next state as a function of the inputs and the current state) and an excitation table (the inputs needed to force a given current-to-next transition), which is the table you read when designing a sequential circuit.
Floating point (IEEE-754): Floating point is a binary format, standardized as IEEE-754, that represents a real number as a sign, a biased exponent, and a fractional mantissa, trading exact even spacing for a huge dynamic range so the same fixed number of bits can hold both very large and very small values.
FPGAs and programmable logic: An FPGA (field-programmable gate array) is a chip full of generic logic blocks (configurable look-up tables plus flip-flops) and programmable wiring that you configure with a stored bit pattern, so the same silicon becomes whatever digital circuit you describe, with no custom fabrication.
From a truth table to a real circuit: Any truth table becomes a circuit by writing one AND term for each row whose output is `1` and then OR-ing those terms together, the mechanical recipe that connects a specification to a buildable gate network.
From counting in binary to adding: Binary addition follows the same carry rule you use in decimal: add each column, and when a column overflows its single digit, carry into the next column, which is the paper procedure an adder turns into gates.
From transistors to gate symbols: A gate symbol is a verified transistor circuit boxed up as one reusable block with a name and a truth table, so that larger designs can be drawn and reasoned about in terms of gates instead of individual transistors.
Full adder: A full adder adds three bits, two operands plus a carry-in, producing a Sum and a carry-out. Chaining one full adder per bit position is exactly how a CPU adds multi-bit numbers.

G

Gated D latch: A gated D latch stores one bit using a single Data input and an Enable input. While Enable is high the output follows D (transparent), and when Enable goes low the latch holds the last value of D. It removes the SR latch's forbidden input combination.
Gray code: Gray code is a binary numbering in which consecutive values differ in exactly one bit, which removes the transient glitches ordinary binary counting causes when several bits flip at the same time.

H

Half adder: A half adder adds two single bits and produces a Sum (their XOR) and a Carry (their AND). It is the first arithmetic circuit, built directly from the logic gates you already have.
Hazards and glitches: A hazard is a momentary wrong output (a glitch) that a logically correct combinational circuit can produce during a single input change because its gates have unequal delays; a static-1 hazard in an AND-OR circuit is removed by adding the redundant consensus term that bridges the two adjacent prime-implicant groups the input change crosses between.
Hexadecimal: Hexadecimal is the base-16 number system, using the digits 0 to 9 then A to F. One hex digit encodes exactly four bits, making it a compact, readable shorthand for the bytes and memory addresses a computer works with.
How a circuit remembers: Feedback is routing a circuit's output back into its own input so the circuit can hold a value after the inputs that set it go away, which is the one idea that turns combinational logic into memory.

I

The instruction register: The instruction register latches the instruction byte fetched from memory and holds it steady while the CPU acts on it, exposing it split into an opcode (what to do) and an operand (what to do it to).

J

JK flip-flop: A JK flip-flop is an edge-triggered one-bit memory cell whose two inputs J and K choose the next state with no illegal combination: J = K = 0 holds, J = 1 K = 0 sets to 1, J = 0 K = 1 resets to 0, and J = K = 1 toggles, giving the characteristic equation Q+ = J·Q' + K'·Q.

K

Karnaugh maps: A Karnaugh map is a truth table rearranged into a grid where adjacent cells differ in a single input bit. Circling the groups of 1s by eye yields the minimal AND-OR expression, a correct circuit with fewer gates than the raw table.

L

Labels and data: A label is a name for a memory address in assembly language; the assembler builds a symbol table mapping each label to the address its line lands at, so you can write LOAD x instead of a hardcoded number and reserve data bytes with a directive like x: .byte 5.
Logic as switches: Logic is built from switches: two switches in series conduct only when both are closed (an AND condition), two switches in parallel conduct when either is closed (an OR condition), and a transistor is simply a switch you close with a voltage instead of a finger.

M

Machine code: Machine code is a program expressed as raw bytes in memory, where each instruction byte splits into an opcode that names an operation and an operand that names its data. Defining that byte-to-meaning mapping is what defines a CPU's instruction set.
Measuring CPU performance: CPU performance is governed by the iron law: CPU time equals the program's instruction count times the average cycles per instruction (CPI) times the clock period, so a design is only faster if it cuts one of those three terms without inflating the others.
The memory hierarchy: The memory hierarchy is the layered arrangement of a computer's storage, from a few fast registers at the top through cache and main memory down to disk, where each level down is larger and cheaper per bit but slower, so a small amount of fast memory sits in front of a large amount of slow memory.
Memory-mapped I/O: Memory-mapped I/O connects a peripheral's control and data registers to specific memory addresses, so a CPU reads and writes devices with the same LOAD and STORE instructions it uses for RAM, needing no special I/O opcodes.
Memory: RAM: RAM is a bank of registers paired with an address decoder: the address selects one cell, a write stores the data bus into it, and a read drives that cell's value back onto the bus through a tri-state. It is where a program and its data live.
Metastability and synchronizers: Metastability is the unstable in-between state a flip-flop can enter when its data input changes too close to the clock edge (a setup or hold violation), where the output hovers at an invalid voltage and resolves to a clean 0 or 1 only after an unpredictable extra delay; the probability it is still undecided decays exponentially with waiting time, and a two-flip-flop synchronizer keeps that resolving state away from the rest of the circuit.
Microcode: Microcode is a technique where the control unit is a small memory (a control ROM) whose stored words are the control-line patterns for each micro-step, so the CPU's instruction set is defined by reprogrammable firmware rather than by fixed gates.
The MOSFET switch: A MOSFET (metal-oxide-semiconductor field-effect transistor) is a switch with three working terminals (gate, source, drain) whose insulated gate voltage decides whether a conducting channel forms between the source and drain; because the gate is insulated it draws almost no steady current.
The multiplexer: A multiplexer (mux) is a data selector: its select inputs choose which one of several data inputs is passed through to the single output. It is the switch that decides which source drives a wire or bus.
The multiplexer as a universal logic element: A multiplexer is a universal logic element: a 2^n-to-1 mux with the n input variables on its select lines implements any n-variable boolean function, because wiring each data input to that function's truth-table output makes the mux a direct truth-table lookup.

N

NAND: A NAND gate outputs 0 only when both of its inputs are 1, and 1 in every other case. It is called universal because every other logic gate can be built from NAND gates alone.
Negative numbers and subtraction: Two's complement encodes negative numbers so the same adder can subtract: to compute A minus B, add A to the bitwise-inverted B with a carry-in of 1. Adding one XOR gate per bit turns a plain adder into a combined adder/subtractor.
NMOS: the strong-0 switch: An NMOS transistor conducts when its gate is a 1, and it passes a strong (full-rail) 0 but only a weak 1 that stops a threshold voltage short of the supply, which is why NMOS is always used to pull an output down toward ground.
NOR: A NOR gate outputs 1 only when both inputs are 0. It is the topological mirror of NAND, with series PMOS pulling up and parallel NMOS pulling down, and like NAND it is universal.
NOR is universal too: NOR is a universal gate: using only NOR gates you can build NOT, OR, AND, and every other logic function, so any digital circuit can be made from NOR alone, just as it can from NAND alone.
NOT: A NOT gate, or inverter, outputs the opposite of its input: 0 becomes 1 and 1 becomes 0. It is the simplest CMOS gate, just one PMOS and one NMOS transistor working in opposition.
Number bases and base conversion: Base conversion rewrites the same number in a different base by regrouping its value into that base's place values: divide by the base and collect remainders (or subtract the largest place value at a time), and group binary digits by 3 for octal or by 4 for hexadecimal.

O

Octal: Octal is base 8: each octal digit runs 0 to 7 and stands for exactly three binary bits, making it a compact shorthand for binary that predates hexadecimal and still appears in Unix file permissions and some legacy encodings.
An opcode becomes control lines: Decoding an instruction is a table lookup from its opcode to the exact set of enable, load, and function control lines to raise, so the control unit is simply a mapping from each opcode to one row of control signals.
OR: An OR gate outputs 1 when at least one of its inputs is 1. In CMOS it is built as a NOR gate followed by an inverter, mirroring how AND is built from NAND.
Overflow and the carry flag: Overflow is when an arithmetic result does not fit in the available bits. The carry flag (carry out of the top bit) signals it for unsigned numbers, while the overflow flag signals it for signed two's-complement numbers, where the sign bit ends up wrong.

P

Pipelining: Pipelining overlaps the execution of several instructions by splitting the datapath into stages (classically fetch, decode, execute, memory, write-back) separated by pipeline registers, so that while one instruction decodes the next is fetched, raising throughput toward one instruction per cycle even though each instruction still takes several cycles from start to finish.
PMOS: the strong-1 switch: A PMOS transistor conducts when its gate is a 0, and it passes a strong (full-rail) 1 but only a weak 0 that stops a threshold voltage short of ground, which is why PMOS is always used to pull an output up toward the power supply.
The priority encoder: A priority encoder is a combinational circuit that outputs the binary index of the highest-numbered active input, resolving the case where several request lines are high at once, and adds a 'valid' output that is 1 whenever any input is active.
Processes and rising_edge: A VHDL process is a block of statements that re-evaluates when a signal in its sensitivity list changes, and the pattern 'if rising_edge(clk)' inside it describes edge-triggered sequential logic, synthesising to a D flip-flop or register.
The program counter: A counter is a clocked circuit that advances through a fixed sequence of values one step per clock edge; a ripple (asynchronous) counter chains toggle flip-flops so each stage clocks the next, a synchronous counter clocks every flip-flop from one common clock so all bits update together, and a program counter is the synchronous counter a CPU uses to hold the address of the next instruction.
The program counter: The program counter (PC) is a register that holds the memory address of the next instruction to fetch; it increments by one each instruction so the CPU walks through memory in order, and it can be loaded with a new address so a jump can redirect execution.
Pull-down networks: A pull-down network is a group of NMOS transistors connecting an output to ground, arranged so it forms a conducting path (pulling the output to 0) for exactly the input combinations where the output should be 0, with series transistors giving an AND condition and parallel transistors giving an OR condition.
Pull-up networks: A pull-up network is a group of PMOS transistors connecting the power supply to an output, wired as the exact dual of the pull-down network (series swapped for parallel), so it drives the output to 1 for precisely the input combinations where the pull-down does not conduct.

Q

Quine-McCluskey minimization: Quine-McCluskey is a tabular, exhaustive algorithm for minimizing a boolean function: it systematically combines minterms that differ in one bit to find every prime implicant, then uses a prime-implicant chart to select a minimum-cost cover, succeeding where Karnaugh maps become unreadable past five or six variables.

R

Reading a multi-gate schematic: A multi-gate circuit is built by feeding the output of one gate into the input of another, and reading its schematic means tracing each wire (net) from the single source that drives it to every gate input that consumes it.
Register bit: A register bit is a D flip-flop plus a write-enable: when enable is high it loads new data on the clock edge, and when enable is low it feeds its own output back to hold the stored bit. It is the one-bit storage cell a register is made of.
The register file: A register file is a small array of registers with several independent read and write ports addressed by register number, so a datapath can read two source operands and write one result in the same clock cycle.
Reset: starting from a known state: Reset is an input that forces a circuit's flip-flops to a known starting value, needed because a flip-flop powers up in an unpredictable state; a synchronous reset takes effect only on the next clock edge, while an asynchronous reset takes effect immediately regardless of the clock.
ROM and PLA: logic as a lookup: A ROM or PLA implements a combinational logic function as stored data rather than gates: a ROM keeps the whole truth table (the output word at every input address), while a PLA keeps only the product terms of the function's sum-of-products form.

S

The seven-segment display decoder: A seven-segment display decoder is a combinational circuit that maps a 4-bit binary-coded-decimal input (the digits 0 to 9) to seven outputs named a through g, each driving one bar of the numeral so the lit bars spell the digit.
Shift registers: A shift register is a chain of flip-flops in which each flip-flop's output feeds the next one's input, so on every clock edge every stored bit moves one position along the chain. It shifts data one step per clock and converts between serial and parallel form.
Sign extension: Sign extension is how a two's-complement number is widened to more bits without changing its value: copy the sign bit (the top bit) into all the new high bit positions, so a negative number stays negative rather than becoming a large positive value.
Signals and std_logic: std_logic is VHDL's standard wire type, holding the values '0', '1', 'Z' (high-impedance) and 'X' (unknown/contention), the same four logic values a probe reads in digiwleea, used for both ports and internal signals.
Signals: 0, 1, Z, X: A digital wire can carry four states: 0 (driven low), 1 (driven high), Z (floating, driven by nothing), and X (contention, driven high and low at once). Telling them apart is essential to reading and debugging a circuit.
SR latch: An SR latch is the simplest memory element: cross-coupled gates feed each output back to the other's input, so the circuit holds its last state after the Set and Reset inputs return to 0. It is how a circuit first gains the ability to remember.
SRAM vs DRAM: SRAM (static RAM) holds each bit in a six-transistor cross-coupled latch, making it fast and stable but large, while DRAM (dynamic RAM) holds each bit as charge on one capacitor guarded by one transistor, making it dense and cheap but requiring periodic refresh, which is why caches use SRAM and main memory uses DRAM.
State minimization and encoding: State minimization is the process of merging the equivalent states of a finite state machine (states that produce the same outputs and transition to equivalent states for every input) so the machine uses as few states, and therefore as few flip-flops, as possible; the related state assignment chooses a binary code for each remaining state, which fixes how complex the next-state and output logic becomes.
Synchronous counters: A synchronous counter is a counter in which every flip-flop shares one common clock so all bits update on the same edge, and a count-enable AND chain toggles bit k only when the enable and every lower bit are 1; a carry-out lets counters cascade, a direction control makes it count up or down, and a decoded synchronous clear or load makes it count through a chosen modulus.

T

T flip-flop: A T flip-flop is an edge-triggered one-bit memory cell with a single input T that either holds the stored bit (T = 0) or flips it to the opposite value on each clock edge (T = 1), giving the characteristic equation Q+ = T XOR Q; held at T = 1 it divides the clock frequency by two, which makes it the building block of binary counters.
Testbenches: A Verilog testbench is a module with no ports that instantiates the design under test, drives its inputs over simulated time inside an initial block, and observes the outputs with $display or $monitor (ending on $finish), so a simulator can verify the design's logic before it is built.
Testbenches: simulating a design: A VHDL testbench is a separate, non-synthesisable design that instantiates the circuit under test, applies a sequence of input stimuli over time, and uses assert statements to check the outputs, the textual equivalent of sweeping inputs and reading the waveform in a simulator.
Timing: delay and the clock speed limit: Propagation delay is the small time a gate takes to update its output after its inputs change. The longest delay path between clocked elements (the critical path), plus the flip-flop's setup time, sets the minimum clock period and therefore the maximum clock frequency.
Tracing a program: A program trace hand-executes a program one step at a time, following the fetch-decode-execute cycle and watching the registers and bus change. Tracing a short LOAD, ADD, STORE, HALT program shows the accumulator CPU actually computing a sum.
The transistor: A transistor is a switch you control with a voltage: a small voltage on its gate decides whether current can flow through it. Every logic gate, and ultimately a whole CPU, is built from these voltage-controlled switches.
Transistor count and sizing: A static CMOS gate uses two transistors per input (one NMOS, one PMOS), and because a transistor's drive current grows with its width, designers make PMOS pull-ups wider than NMOS pull-downs and widen transistors stacked in series so the gate switches at a balanced, predictable speed.
The transmission gate: A transmission gate is an NMOS and a PMOS wired in parallel and driven by complementary control signals, so that when enabled it passes both a strong 0 (through the NMOS) and a strong 1 (through the PMOS) in either direction, and when disabled it presents a high-impedance open switch.
The transparency problem: The transparency problem is that a level-enabled latch follows its input for the entire time it is open, so capturing a value at one precise instant requires chaining two latches into an edge-triggered flip-flop.
Tri-state buffers and the shared bus: A tri-state buffer can drive its output high, drive it low, or disconnect entirely into a high-impedance (Z) state. That third state lets many components share one bus by taking turns driving it, which is how a CPU moves data between blocks.
Truth tables: A truth table lists the output a logic function produces for every possible combination of its inputs. It is the complete, unambiguous specification of a circuit: what you design from and what you verify against.
Two kinds of circuit: A combinational circuit produces outputs that depend only on its current inputs, while a sequential circuit's outputs also depend on stored history, and distinguishing them tells you whether the circuit needs memory and a clock.
Two's complement: Two's complement is the standard way computers store signed integers: the most significant bit carries a negative weight of -2^(n-1), so to negate a number you invert all its bits and add one, and a single adder then handles both addition and subtraction.

V

Verilog: the other HDL: Verilog is a hardware description language (HDL) that, like VHDL, describes digital hardware as text so it can be simulated and synthesised into real gates; its unit of design is the module (a named block with an input/output port list), and its C-like syntax makes it the most common HDL in US chip design.
Virtual memory: Virtual memory gives each program its own large, private address space that hardware maps onto the smaller physical RAM through a page table, with a translation lookaside buffer (TLB) caching recent mappings, so programs address memory as if they owned it all.
Von Neumann vs Harvard: The von Neumann architecture stores instructions and data in a single memory sharing one bus, while the Harvard architecture uses separate memories and buses for instructions and data, letting the CPU fetch an instruction and access data at the same time.

W

What is an HDL?: A hardware description language (HDL) such as VHDL or Verilog is a text language for describing the structure and behavior of a digital circuit, which a synthesis tool then turns into real logic gates on an FPGA or ASIC.
When logic starts to count: Adding two bits is nothing more than an XOR gate for the sum and an AND gate for the carry, which is the moment logic gates stop being abstract truth functions and start performing arithmetic.
Why CMOS sips power: CMOS uses very little power because in any steady state exactly one of its complementary networks conducts, so there is no direct path from the power supply to ground and almost no static current; the energy it does use is spent charging and discharging wires only while outputs switch.
Widening a 1-bit circuit: Widening a circuit to a byte means placing eight copies of the 1-bit version side by side, each handling one bit and all sharing the same control lines, the bit-slice replication pattern behind every multi-bit block.
Wires, nets, and junctions: A net is the set of everything electrically connected by wire. Wires that cross only join where a junction dot marks them, a signal can branch to many gate inputs safely, but driving one net from two outputs at once causes contention.
Wires, registers, and vectors: In Verilog a wire carries a continuously-driven value while a reg holds a value assigned inside a procedural block; either can be a single bit or a vector such as [7:0] for a multi-bit bus, and every bit is four-state (0, 1, x for unknown, z for high-impedance).
Wiring blocks into a data path: A datapath is a set of registers and an ALU joined by a shared bus, where control lines decide, each cycle, which one block drives the bus and which blocks read from it.
Writing a program: Writing a program for the accumulator CPU means laying out instructions and data in memory so a straight-line sequence of LOAD, ADD, and STORE computes and saves a result; the machine runs top to bottom once, and adding control flow (loops and decisions) requires a jump instruction that changes the program counter.

X

XNOR and the equality comparator: An XNOR (exclusive-NOR) gate outputs 1 exactly when its two inputs are equal, so it is a one-bit equality detector. ANDing one XNOR per bit builds an equality comparator that reports whether two multi-bit numbers match.
XOR: An XOR (exclusive-OR) gate outputs 1 exactly when its two inputs differ. No single static CMOS gate computes it, so it is built from a small network of NAND gates, and it forms the core of binary addition.
XOR at the transistor level: XOR outputs 1 exactly when its two inputs differ, and because it has no compact single-stage static CMOS network it is built either from several NAND gates or, more compactly, from transmission gates that pass A when B is 0 and NOT A when B is 1.

#

An 8-bit register: An 8-bit register is eight register bits sharing one clock and one write-enable, so it loads a whole byte off the bus when enabled and holds it otherwise. It is the basic storage box of a CPU.