From logic to silicon
The detailed, transistor-by-transistor build-along: how a logical structure (an AND condition, an OR condition, a whole Boolean expression) becomes a network of MOSFET switches. Meet the NMOS and PMOS switches on their strong sides, build pull-down and pull-up networks, wire the inverter, NAND, NOR, AND, OR, and XOR one transistor at a time, and see why complementary CMOS reaches full rails at almost no static power before you step up to gate symbols.
Logic as switchesThe atom every gate is made ofA switch is the atom of logic: switches in series compute AND, switches in parallel compute OR, and that is the whole idea a transistor automates.The MOSFET switchGate, source, drain, and the insulated handleA MOSFET is the voltage-controlled switch of digital chips: an insulated gate whose voltage builds or removes a conducting channel between the source and drain.NMOS: the strong-0 switchCloses on a gate 1, and pulls firmly to groundAn NMOS conducts when its gate is 1 and passes a full-strength 0 but only a weak, threshold-dropped 1, which is why it always belongs in the pull-down network.PMOS: the strong-1 switchCloses on a gate 0, and pulls firmly to powerA PMOS conducts when its gate is 0 and passes a full-strength 1 but only a weak, threshold-lifted 0, which is why it always belongs in the pull-up network.Pull-down networksWiring NMOS to detect when the output should be 0A pull-down network is NMOS transistors wired between the output and ground so that they conduct for exactly the input rows where the output must be 0, using series for AND and parallel for OR.Pull-up networksThe PMOS dual that drives the output to 1A pull-up network is PMOS transistors wired from power to the output as the exact structural dual of the pull-down, so it conducts on precisely the rows where the pull-down does not.The complementary pairWhy exactly one network is ever onStacking a PMOS pull-up over a dual NMOS pull-down makes a complementary gate: for every input exactly one network conducts, so the output is always driven to a full-strength 0 or 1.Why CMOS sips powerNo steady path from power to groundA static CMOS gate draws almost no power when idle because exactly one network is on, leaving no path from power to ground; nearly all its energy is spent only while switching.Build the inverterTwo transistors, traced row by rowThe inverter is one PMOS pull-up over one NMOS pull-down sharing an input; tracing both input values shows exactly one transistor conducting and the output landing on the opposite rail.Build NAND and NORFour transistors each, and exact mirror imagesNAND is series NMOS with parallel PMOS and NOR is its exact mirror (parallel NMOS with series PMOS); both use four transistors and both are naturally inverting.AND and OR: the price of not invertingWhy the friendly gates cost an extra stageStatic CMOS gates are naturally inverting, so AND is a NAND followed by an inverter and OR is a NOR followed by an inverter, each costing six transistors and two stages instead of four and one.The transmission gateAn NMOS and PMOS in parallel that pass any valueA transmission gate wires an NMOS and a PMOS in parallel with opposite control signals so it passes a full-strength 0 and 1 in either direction, or switches to high-Z when off.XOR at the transistor levelThe gate with no simple series-parallel networkXOR has no compact single-stage CMOS network, so it is built either from a handful of NAND gates or, more compactly, from transmission gates that select between A and NOT A using B.Transistor count and sizingHow many transistors, and how wideA static gate takes two transistors per input, and designers widen the slower PMOS and any series-stacked transistors so the gate charges and discharges its load at balanced, predictable speed.From transistors to gate symbolsWhen to stop drawing switchesOnce a gate is built and verified from transistors, we hide the transistors behind a single gate symbol and reason with truth tables, which is the abstraction that makes designing large circuits possible.