Build NAND and NOR
Four transistors each, and exact mirror images
A CMOS NAND is built from two series NMOS pulling down and two parallel PMOS pulling up (output 0 only when both inputs are 1), and a CMOS NOR is its exact mirror with two parallel NMOS and two series PMOS (output 1 only when both inputs are 0); each uses four transistors.
Build it in the lab →Give each of the inverter's two networks a second transistor and you get the two workhorse gates of digital logic: NAND and NOR. They are the naturally cheap CMOS gates (four transistors, one stage of delay), and they are exact mirror images of each other, which makes them the perfect pair for feeling the pull-up/pull-down duality in action. These are the same gates the NAND and NOR lessons treat as logic; here we build and trace the transistors.
NAND: series pull-down, parallel pull-up
NAND should output
0 only when A and B are both 1. "Only when both are 1" is the AND condition, so the pull-down is two NMOS in series: current reaches GND only when both are on. The dual pull-up is two PMOS in parallel: either input being 0 pulls the output to a full 1. Four transistors: A drives one NMOS and one PMOS, B drives the other pair.| A | B | series NMOS | parallel PMOS | F |
|---|---|---|---|---|
| 0 | 0 | off | on | 1 |
| 0 | 1 | off | on | 1 |
| 1 | 0 | off | on | 1 |
| 1 | 1 | on | off | 0 |
1), pulling F to 0. On every other row a parallel PMOS conducts and pulls F to 1. Exactly one network is on per row.A and B each driving one of each. Open it in the lab and confirm only A = B = 1 pulls the output low.NOR: the exact mirror
NOR should output
1 only when A and B are both 0; equivalently, it outputs 0 whenever A or B is 1. "When either is 1" is the OR condition, so the pull-down is two NMOS in parallel: either input being 1 drags the output to 0. The dual pull-up is two PMOS in series: the output reaches 1 only when both inputs are 0. It is NAND with the two networks swapped, series for parallel, top for bottom.| A | B | parallel NMOS | series PMOS | F |
|---|---|---|---|---|
| 0 | 0 | off | on | 1 |
| 0 | 1 | on | off | 0 |
| 1 | 0 | on | off | 0 |
| 1 | 1 | on | off | 0 |
1, pulling F to 0. Only A = B = 0 leaves both NMOS off and lets the series PMOS pull F to 1.Hold the two side by side: NAND = series NMOS, parallel PMOS. NOR = parallel NMOS, series PMOS. Each is the other with series and parallel swapped in both networks. This mirror is the clearest single picture of the series = AND, parallel = OR rule, and both gates are universal, so everything else can be built from either one alone.
Do not mix up which stack is series. The series chain is the network that must have all its transistors on to conduct, and it sits in the pull-down for NAND but in the pull-up for NOR. A frequent error is building "NAND" with parallel NMOS: that is actually a NOR, and its truth table will not match. Trace all four rows before trusting a hand-built gate. Also note NAND is often preferred in practice because its series stack is NMOS (fast electrons), while NOR's series stack is the slower PMOS, so a NOR is comparatively sluggish, a point transistor sizing revisits.
Try it
In your NAND, which two transistors are in series, and why does that give a
0 only when both inputs are 1? Then say what you would change to turn it into a NOR.Answer
Build it in the lab ↗The two NMOS are in series (stacked). Current reaches
GND only when both conduct, which needs both gates at 1, so F is pulled low only in the A = B = 1 row. To make a NOR, swap both networks: put the two NMOS in parallel (so any 1 pulls down) and the two PMOS in series (so only A = B = 0 pulls up). Same four transistors, mirrored topology.Frequently asked
How do you build a NAND gate from transistors?
Put two NMOS in series as the pull-down, so the output goes
0 only when both inputs are 1, and two PMOS in parallel as the pull-up, so the output goes 1 whenever either input is 0. That is four transistors: series-down, parallel-up.How do you build a NOR gate from transistors?
Put two NMOS in parallel as the pull-down, so the output goes
0 whenever either input is 1, and two PMOS in series as the pull-up, so the output goes 1 only when both inputs are 0. It is four transistors and the exact mirror of a NAND.What is the difference between a NAND and a NOR at the transistor level?
They are exact mirrors. NAND has series NMOS (pull-down) and parallel PMOS (pull-up); NOR has parallel NMOS (pull-down) and series PMOS (pull-up). Swapping series for parallel in both networks turns one into the other, and both use four transistors and are universal.
Why is NAND usually faster than NOR in CMOS?
NAND's series stack is made of NMOS, whose electron carriers are fast, while NOR's series stack is PMOS, whose hole carriers are slower. Series transistors are the speed bottleneck, so putting the slower PMOS in series makes NOR comparatively sluggish, which is why designers often prefer NAND.
These inverting gates are the cheap, natural ones. Next: the friendly non-inverting gates, AND and OR, and why they cost an extra stage.
You've got the theory. Now build it from scratch and watch it work.
Build it in the lab →