Designing gates from truth tables
A repeatable method for any static CMOS gate
You can derive any static CMOS gate from its truth table: build an NMOS pull-down network that conducts for exactly the rows where the output is 0, then mirror it with a complementary PMOS pull-up. Series transistors create AND conditions, parallel transistors create OR conditions.
Build it in the lab →From Complementary CMOS you know the skeleton: a PMOS pull-up network to
VCC and a complementary NMOS pull-down network to GND, never both on at once. And from truth tables you know how to write down exactly what a gate should do. This lesson is the method that turns one into the other, filling the skeleton in from the table. Once you have it, designing a new gate stops being a puzzle and becomes a procedure you can repeat for anything, including every gate in your CPU.Why the pull-down is NMOS and the pull-up is PMOS
That skeleton is not an arbitrary convention: it follows from what each transistor is physically good at. An NMOS passes a
0 cleanly but a 1 only weakly, so it delivers a solid, full-strength 0, a strong 0. A PMOS is the mirror image: it passes a 1 cleanly but a 0 weakly, so it delivers a strong 1. To drag the output firmly down to GND you want that strong 0, so the pull-down is always built from NMOS. To push the output firmly up to VCC you want the strong 1, so the pull-up is always built from PMOS. Each transistor is used on its strong side, and that is the whole reason the two networks are assigned the way they are.One consequence falls straight out of this, and you will lean on it constantly: the NMOS pull-down can only ever pull the output toward
0, and it switches on for exactly the input combinations that make its network conduct. So the network you build detects a condition, and the output is the logical inverse of that condition. Every static CMOS gate is therefore naturally inverting: it always carries that little bubble. NAND, NOR, and the inverter are the cheap, natural shapes; a plain AND or OR costs an extra inverter stage on top.A classic mistake is to reuse the same transistor type in both networks, or to let an NMOS pull the output up toward
VCC. It half-works in a quick simulation but delivers a degraded weak 1: the output never reaches full VCC, static current leaks, and switching is sluggish. Keep every transistor on its strong side: NMOS only in the pull-down, PMOS only in the pull-up.The design recipe
- Write out the truth table for the gate you want.
- Circle every row where the output is
0. Those rows define exactly when the pull-down NMOS network must conduct. - Ask what combination of input values causes each
0row. Each row gives you one condition. - If the output is
0only when both inputs are1together, the NMOS transistors go in series (both must close for current to flow). Series = AND. - If the output is
0when either input alone is1, the NMOS transistors go in parallel (any one closing is enough). Parallel = OR. - Build the PMOS pull-up as the structural complement: swap every series group for a parallel group and vice versa. (PMOS already inverts each input, so the complement falls out automatically.)
- Verify: trace both networks for every input row and confirm exactly one forms a complete conducting path.
Series = AND, parallel = OR. Series NMOS means *all* its conditions must be true at once before current flows. Parallel NMOS means *any* one condition is enough. Burn this in: it is the single idea behind every gate shape you will draw.
Worked example: NOR
NOR outputs
0 whenever either A or B is 1. That is the OR condition, so the pull-down is two NMOS in parallel: either one conducting drags the output low. The pull-up is the complement, two PMOS in series, so VCC reaches the output only when A and B are both 0.| A | B | F |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
A and B must be 0), two NMOS in parallel pulling down (either being 1 is enough). Open it in the lab and watch which network lights up per row.Compare NOR and NAND
NAND outputs
0 only when both A and B are 1, so its pull-down is two NMOS in series and its pull-up is two PMOS in parallel. NOR is the exact mirror. Putting them side by side is the clearest way to feel the series/parallel rule:- NAND: NMOS in series (pull down only when
AANDBare1), PMOS in parallel (pull up whenAis0ORBis0). - NOR: NMOS in parallel (pull down when
Ais1ORBis1), PMOS in series (pull up only whenAANDBare0).
NAND: F
= (AB)' NOR: F
= (A + B)'
Compound gates: read the transistors off a Boolean expression
NOR and NAND each use a single operator, but real gates freely mix AND and OR, and you can read the entire transistor arrangement straight off a sum-of-products expression. The rule is the one you already have, applied term by term: a product (an AND) becomes transistors in series, and a sum (the OR that joins terms) becomes branches in parallel. Build that arrangement in NMOS for the pull-down, then draw the PMOS pull-up as its exact dual, swapping every series group for parallel and every parallel group for series. Because the gate inverts, the expression you wire into the pull-down is the condition for the output to be
0.Take the compound gate that outputs
NOT(A·B + C). This is an AND-OR-Invert gate (an AOI): two inputs are AND'd, that result is OR'd with a third input, and the whole thing is inverted, all inside one gate with no separate inverter. The part inside the NOT, the expression A·B + C, is precisely the condition that must pull the output to 0, so it is the pull-down expression.AOI: F
= NOT ( (AB) + C )
= (A·B + C)'
- Pull-down (NMOS). The product
A·Bis an AND, soAandBgo in series. That pair is OR'd withC, so it sits in parallel with a loneCtransistor. Three NMOS, arranged as (Ain series withB) in parallel withC. - Pull-up (PMOS). Take the dual: every series becomes parallel and every parallel becomes series, keeping the same input on each gate. The
A,Bseries pair becomesAin parallel withB, and its being-in-parallel-with-Cbecomes series withC. Three PMOS, arranged as (Ain parallel withB) in series withC. - Total: six transistors. For every one of the eight input rows, exactly one of the two networks forms a complete path, so the output is always driven, never floating and never shorted.
| A | B | C | A·B+C | F |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 |
A series B) parallel C conducts on exactly the five F = 0 rows (every row with C = 1, plus the A = B = 1 row); the dual pull-up (A parallel B) series C conducts on the three F = 1 rows.One honesty check about the gate inputs: an NMOS turns on when its gate input is
1, so a plain literal like A in the pull-down maps directly to an NMOS gated by A. If a term instead needs a complemented literal such as NOT A, you drive that transistor's gate with the already-inverted signal (add one inverter to produce it). The series and parallel shape never changes, only the signal sitting on the gate. The example above uses A, B, and C uncomplemented, so it needs no extra inverters.The dual is a purely mechanical flip: never re-derive the pull-up from scratch. Draw the NMOS pull-down from the expression, then turn every series into parallel and every parallel into series to get the PMOS pull-up. Any sum-of-products, with any number of terms, becomes transistors this way, which is how a single compact AOI (or its sibling OAI, OR-AND-Invert) implements a whole chunk of logic in one gate instead of a stack of separate NANDs.
Try it
Design the pull-down for a 2-input gate whose output is
0 only when A = 1 and B = 0 (and 1 for every other input). Series or parallel? And which form of each input drives the NMOS gates?Answer
Only one
0 row, and it needs both conditions at once (A = 1 AND B = 0), so the pull-down is two NMOS in series. A = 1 turns its NMOS on directly, but B = 0 must turn its NMOS on, so feed that one **NOT B**. Series NMOS with gates A and NOT B: the output pulls low only in that single row. The pull-down *detects* the condition A AND NOT B, but a CMOS gate always inverts, so the gate's output is its complement, NOT(A AND NOT B) = A' OR B (it is 0 only in that one row and 1 everywhere else, exactly as asked).The method scales to any number of inputs and any mix of conditions: a three-input AND adds a third series transistor, a three-input OR adds a third parallel one, and complex gates combine both in one network. You now have everything you need to design the gates in the next group, starting with the inverter and the universal NAND. (And once a gate works, a Karnaugh map at the end of that group shows how to make it as small as possible.)
Spot the fault
A1B1pull-up1pull-down1FX
Look at F
Short (X)
On this input row both the pull-up and pull-down networks conduct, so
F is tied to VCC and GND at once and reads X. The two networks must be exact complements: rework the series/parallel arrangement so that for every row exactly one network forms a conducting path.Frequently asked
How do you design a CMOS gate from a truth table?
Circle every row where the output is
0: those rows define when the NMOS pull-down network must conduct. Build that pull-down from the 0 conditions, then mirror it with a complementary PMOS pull-up (swap every series group for parallel and vice versa). Finally verify by tracing both networks for every row, confirming exactly one forms a complete conducting path.When do transistors go in series versus parallel?
Series = AND, parallel = OR. If the output is
0 only when both inputs are 1 together, the NMOS transistors go in series (both must close before current flows). If the output is 0 when either input alone is 1, the NMOS transistors go in parallel (any one closing is enough).What is the difference between a NOR and a NAND gate's transistor layout?
They are exact mirrors. NAND outputs
0 only when both inputs are 1, so its pull-down is two NMOS in series and its pull-up two PMOS in parallel. NOR outputs 0 when either input is 1, so its pull-down is two NMOS in parallel and its pull-up two PMOS in series.Why is the pull-down network made of NMOS and the pull-up of PMOS?
Because each transistor is used on its strong side. An NMOS passes a
0 cleanly (a strong 0) but a 1 only weakly, so it is ideal for pulling the output down to GND. A PMOS passes a 1 cleanly (a strong 1) but a 0 weakly, so it is ideal for pulling the output up to VCC. Swapping them would leave the output at a degraded weak level and leak static current.What is an AND-OR-Invert (AOI) gate?
An AOI gate computes the inverse of a sum-of-products in one static CMOS gate: some inputs are AND'd (product terms), those products are OR'd together, and the whole result is inverted, for example
NOT(A·B + C). In the NMOS pull-down each product is a series group and the products sit in parallel, and the PMOS pull-up is the exact dual. One compact AOI replaces several separate gates.Why are static CMOS gates always inverting?
The NMOS pull-down can only pull the output toward
0, and it conducts for exactly the input combinations its network detects, so the output is the logical inverse of that condition. That is why NAND, NOR, and the inverter are the natural, cheap shapes, while a non-inverting AND or OR needs an extra inverter stage on top.You've got the theory. Now build it from scratch and watch it work.
Build it in the lab →