Gated D latch
One data input, one enable
A gated D latch stores one bit using a single Data input and an Enable input. While Enable is high the output follows D (transparent), and when Enable goes low the latch holds the last value of D. It removes the SR latch's forbidden input combination.
Build it in the lab →The SR latch can store a bit, but it makes you drive two inputs carefully and dodge the forbidden
S=R=1 state. This lesson wraps that latch in a tiny steering network built from AND and NOT, so you control it with one Data line and one Enable line, and the forbidden state becomes impossible by construction.Building the steering network
Two AND gates feed the SR latch's
S and R inputs:S = D ∧ EN
R = (¬D) ∧ EN
Because
D and NOT D are always opposite, S and R can never both be 1: the forbidden combination simply cannot occur. And when EN=0, both AND gates output 0 regardless of D, giving S=0, R=0, which is precisely the SR latch's hold state.That is the whole trick:
EN=0 forces S=0, R=0, and the latch holds automatically. No special storage circuitry is added; the SR latch you already built does the remembering.Transparent behavior over time
EN=0,Danything:S=0, R=0.Qholds its last value.- Raise
EN=1withD=1:S=1, R=0, the latch sets,Q=1. The output followedD. - Still
EN=1, changeD=0:S=0, R=1, the latch resets,Q=0.QfollowedDimmediately. - Drop
EN=0:S=0, R=0.Qholds 0 even asDkeeps changing. The window has closed. - Raise
EN=1again withD=1:Qcaptures the newDand goes to 1. - Drop
EN=0:Qholds 1. OnlyDat the instantENfell still matters.
The latch is transparent while
EN=1: any glitch on D passes straight to Q in real time. If D bounces before you lower EN, Q bounces too. That weakness is the entire reason the D flip-flop exists.An analogy:
EN is a window. While it is open (EN=1) the latch watches D and Q copies it live, draughts and all. When the window shuts (EN drops to 0) it freezes the last thing it saw and stops watching. Useful, but a flip-flop will want the window open for only an instant.D and NOT D into the SR core depending on EN. Open it in the lab and watch Q track D only while EN is high.Try it
With
EN = 1 and D = 1, Q is 1. You drop EN = 0, then change D to 0. What is Q? Then you raise EN = 1 again. Now what is Q?Answer
While
EN = 0 the latch holds, so changing D does nothing: Q stays 1. The moment you raise EN = 1 it becomes transparent again and immediately follows D, which is now 0, so Q drops to 0. The latch only captures D while its window is open.When you save this as a part for later levels, pin order matters. The simulator orders pins by position (top to bottom on each side), so place
EN and D so their vertical positions match what the next level expects.The gated latch is one step from a flip-flop. Its weakness is the open window: it is transparent for as long as
EN is high. Shrink that window to a single instant, the clock edge, and you get the rock-solid storage element of every CPU. That is the D flip-flop, next.Frequently asked
What is a gated D latch?
A gated D latch stores one bit using a single Data input
D and an Enable input EN. While EN is high the output follows D; when EN goes low it holds the last value of D.How does a D latch remove the SR latch's forbidden state?
It feeds the SR latch through two AND gates:
S = D AND EN and R = (NOT D) AND EN. Because D and NOT D are always opposite, S and R can never both be 1, so the forbidden combination cannot occur.What does it mean that a D latch is transparent?
While
EN = 1 the output Q tracks D in real time, including any glitch on D. The latch is a window: open while EN is high, frozen when EN falls. That live transparency is exactly the weakness the D flip-flop fixes.You've got the theory. Now build it from scratch and watch it work.
Build it in the lab →