HDL
Bridging the circuits you built by hand to professional practice: how engineers describe hardware in VHDL text (entity, architecture, signals, concurrent equations, and clocked processes) and verify it with a testbench before it is synthesised onto an FPGA or ASIC.
What is an HDL?Describing hardware in textA hardware description language like VHDL or Verilog is text that DESCRIBES a circuit, not a program that runs step by step. A synthesis tool turns that description into real gates on an FPGA or ASIC.Entity and architectureThe interface and the insidesA VHDL design has two halves: the entity declares the black-box interface (the named input and output ports), and the architecture describes what is inside it. It is the same split as a custom part's pins versus its internal circuit.Signals and std_logicThe four values a wire can carryVHDL's std_logic type is a wire that can carry the same four values you already meter on the canvas: 0, 1, Z (floating), and X (contention). Ports cross the boundary; internal signals are the wires inside.Concurrent assignmentsCombinational logic as equationsA concurrent signal assignment (F <= ...) is a standing piece of combinational logic: a boolean equation that is always live. You can read one straight off a truth table as the sum of the rows where the output is 1.Processes and rising_edgeDescribing logic that remembersConcurrent assignments describe combinational logic; a clocked process describes sequential logic. The pattern if rising_edge(clk) captures a value on the clock edge, which is precisely a D flip-flop.Testbenches: simulating a designDriving inputs and checking outputsA testbench is VHDL that wraps your design, drives its inputs over time, and checks its outputs with assert. It is the textual version of the waveform/timing view you use in the lab to verify a circuit.Verilog: the other HDLDescribing hardware in a C-like languageVerilog is a hardware description language, like VHDL, but with a terser C-like syntax. It is the dominant HDL in US chip design. The basic unit is the module: a named block with a port list, exactly the entity/architecture idea you saw in VHDL.Continuous assignmentCombinational logic with assignA Verilog continuous assignment (assign F = ...) is a standing piece of combinational logic: a boolean equation that is always live, written with & (AND), | (OR), ~ (NOT), and ^ (XOR). You read one straight off a truth table as the sum of the rows where the output is 1.always @(posedge clk)Describing logic that remembersContinuous assignments describe combinational logic; a clocked always block describes sequential logic. The pattern always @(posedge clk) with a nonblocking <= captures a value on the clock edge, which is precisely a D flip-flop.Wires, registers, and vectorswire vs reg, and multi-bit busesA Verilog wire carries a continuously-driven value; a reg holds a value assigned in a procedural block (and is NOT necessarily a hardware register). Both can be one bit or a vector like [7:0] for a bus, and each bit is 4-state: 0, 1, x (unknown), z (high-impedance).TestbenchesDriving inputs and checking outputsA Verilog testbench is a port-less module that instantiates the design under test, drives its inputs over time in an initial block with # delays, and prints or checks the outputs with $monitor/$display and $finish. It is how you verify logic in simulation before it becomes hardware.FPGAs and programmable logicA blank chip that becomes your circuitProgrammable logic devices (ROMs, PLAs, PALs, CPLDs, and FPGAs) are generic chips you configure to behave like any circuit. An FPGA's core trick is the look-up table: a tiny truth table stored in SRAM, so the same silicon becomes whatever function you load into it.