What is an HDL?
Describing hardware in text
A hardware description language (HDL) such as VHDL or Verilog is a text language for describing the structure and behavior of a digital circuit, which a synthesis tool then turns into real logic gates on an FPGA or ASIC.
So far you have built circuits the way hardware was built for decades: by placing components and drawing wires. You derived each gate from its truth table and wired transistors by hand in designing gates. That is exactly how a chip works, but it does not scale: nobody hand-places the billion transistors in a real processor. Engineers instead describe the circuit in text and let a tool generate the gates. That text is written in a hardware description language, or HDL.
Hardware description, not a program
This is the idea that trips up every newcomer from software: an HDL describes hardware that all exists at once, it is not a recipe of steps that execute in order. When you write
F <= A and B, you are not telling a processor to compute an AND at some moment; you are declaring that a physical AND gate exists, with A and B on its inputs and F on its output, energised continuously. Everything you write happens in parallel, all the time, the same way every gate on your canvas is always live.The single most common mistake is reading HDL like software. A line of C runs once when control reaches it. A line of HDL is a piece of standing hardware. There is no "current line", no top-to-bottom execution of the whole file, and writing two drivers for the same wire does not mean "the second one wins", it means a short (your
X value) just like wiring two outputs together on the canvas.From text to silicon: synthesis
An HDL file is fed to a synthesis tool (Xilinx Vivado, Intel Quartus, and others). Synthesis reads your description, works out the gates and flip-flops it implies, optimises them (much like a Karnaugh map minimises by hand), and maps them onto a target chip: an FPGA (a reconfigurable grid of logic you can reprogram in seconds) or an ASIC (a custom chip etched once in a factory). The same description can target either. You describe *what* the circuit does; the tool decides *which* gates realise it.
An analogy: an HDL is to a circuit what a blueprint is to a building. The blueprint is not the building and it does not "run", it specifies every wall and pipe so a builder (the synthesis tool) can construct the real thing. Two builders might lay the bricks slightly differently, but both produce a structure that matches the blueprint.
VHDL and Verilog
Two HDLs dominate. VHDL is verbose and strongly typed, with explicit declarations and a strict notion of signal types (it came out of a 1980s US Department of Defense project). Verilog is terser and looks more C-like. They express the same hardware; the choice is mostly regional and institutional. This short track teaches VHDL because its explicit
entity / architecture split maps cleanly onto something you already know: the interface of a part versus its insides.library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port (
A : in std_logic;
B : in std_logic;
F : out std_logic
);
end entity;
architecture rtl of and_gate is
begin
F <= A and B;
end architecture;A, B, F are its pins; the single assignment is the gate itself. The next lesson takes this apart line by line.Why this matters: every real digital chip you have ever used was described in an HDL, not drawn by hand. The transistor-level understanding you built here is exactly what lets you read HDL correctly, because you know what hardware each line actually becomes. You are not learning a new way to think, you are learning to write down the thinking you already do.
Check yourself
A friend coming from Python says: "In VHDL, if I write
F <= A and B and then F <= A or B below it, the second line overwrites the first, right?" What is wrong with that intuition?Answer
It treats HDL like software running top to bottom. Both lines are standing hardware that exist at the same time, so you have wired two gates' outputs onto the same wire
F: that is a short, not an overwrite. The result is the X (contention) value, exactly like connecting two part outputs together on the canvas. To choose between two values you need a real selector circuit (a multiplexer), not a second assignment.Frequently asked
What is a hardware description language (HDL)?
An HDL such as VHDL or Verilog is a text language for describing a digital circuit's structure and behavior. A synthesis tool reads it and produces real logic gates and flip-flops on an FPGA or ASIC. It describes hardware that exists all at once, it is not a program that runs line by line.
Is VHDL a programming language?
No. VHDL looks like code but it describes hardware, not a sequence of steps. Every statement becomes a piece of standing circuitry that operates continuously and in parallel, so there is no top-to-bottom execution of the file the way there is in C or Python.
What is the difference between VHDL and Verilog?
Both are HDLs that describe the same kind of hardware. VHDL is verbose and strongly typed with explicit declarations; Verilog is terser and more C-like. The choice is mostly regional and institutional rather than technical.
What does synthesis mean in HDL?
Synthesis is the step where a tool (such as Vivado or Quartus) reads your HDL description, works out the gates and flip-flops it implies, optimises them, and maps them onto a target chip, either a reprogrammable FPGA or a custom ASIC.
Every lesson here builds toward one thing: a working CPU, from the transistor up.
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