Why CMOS sips power

No steady path from power to ground

5 min read

CMOS uses very little power because in any steady state exactly one of its complementary networks conducts, so there is no direct path from the power supply to ground and almost no static current; the energy it does use is spent charging and discharging wires only while outputs switch.

Builds onThe complementary pair

From the complementary pair you know that in any settled state exactly one of a gate's two networks conducts. Follow that fact to its conclusion about power and you find the reason CMOS beat every earlier logic family and now runs essentially every chip on the planet. The idea is simple: if there is no unbroken path from VCC to GND, no steady current flows, and current times voltage is power.

Static power: almost none

Consider a CMOS gate sitting with fixed inputs, not switching. Exactly one network is on. If the pull-down is conducting, the pull-up is open; if the pull-up is conducting, the pull-down is open. Either way, the chain from VCC through the gate to GND is broken somewhere. No complete path means no steady current from supply to ground, so the gate burns almost no power just holding its output. This idle draw is the static power, and in CMOS it is tiny (only a little unavoidable leakage through transistors that are nominally off).

Contrast the older approach. Some earlier logic families held their output with a plain resistor pulling toward one rail while a transistor pulled toward the other. Whenever the output was in one of its two states, that resistor and transistor formed a live path from VCC to GND and burned power continuously, even doing nothing. CMOS replaced the resistor with a complementary transistor network that simply *opens*, cutting the path entirely. That is the leap.

Dynamic power: paid only when switching

So where does a CMOS chip's power actually go? Almost all of it is spent switching. Every wire and every gate input has a small capacitance (recall the gate is like a tiny capacitor, from the MOSFET). Each time an output flips from 0 to 1, the pull-up must charge that capacitance up to VCC; each time it flips back to 0, the pull-down drains it to GND. Charging and discharging those tiny capacitors is where the energy goes.

That gives the rule of thumb for CMOS power: it grows with how much capacitance you switch, with the square of the supply voltage, and with how often you switch (the clock frequency).

P(dynamic) ≈ C · V² · f

Here C is the capacitance being switched, V is the supply voltage, and f is the switching frequency. Two design levers fall straight out of it: lowering the supply voltage helps a lot (it enters squared), and a gate that is not switching costs almost nothing, which is why chips aggressively gate the clock off to idle blocks. A brief extra sip happens during each transition, when the input is midway and both networks conduct for an instant (short-circuit current), but with sharp input edges this is a small correction next to the capacitor charging.

The headline: CMOS pays for change, not for state. Holding a value is nearly free; flipping it costs energy. This is why a phone can hold data in memory for days on a small battery yet heats up during heavy computation, and why lowering voltage and idling unused blocks are the first tools for saving power.

"Almost no static power" is not "zero." Real transistors leak a little even when off, and as chips shrank to billions of transistors this leakage grew into a serious fraction of total power. And a floating gate input defeats the whole argument: hovering near the threshold, it leaves both networks partly on, creating exactly the VCC-to-GND path CMOS is supposed to avoid, so it wastes power and runs hot. Always drive every input to a firm 0 or 1.

Check yourself

A CMOS gate's inputs are steady and its output is holding a 1. Roughly how much current flows from VCC to GND through the gate, and why? What if you halve the supply voltage on a busy chip?

Frequently asked

Why does CMOS use so little power?

Because in any steady state exactly one of its complementary networks conducts, so there is no complete path from the power supply to ground and almost no static current flows. A CMOS gate spends energy mainly while switching, charging and discharging the small capacitance of wires and gate inputs, not while holding a value.

What is the difference between static and dynamic power in CMOS?

Static power is the tiny idle draw when the gate is not switching (just transistor leakage, since no path connects power to ground). Dynamic power is the energy spent while switching, dominated by charging and discharging load capacitance and scaling roughly as capacitance times voltage squared times frequency.

How can you reduce a CMOS chip's power consumption?

Lower the supply voltage (power scales with voltage squared), switch less often or gate the clock off to idle blocks (dynamic power scales with frequency), and reduce the capacitance being switched. Because holding a value is nearly free, keeping unused logic quiet saves the most.

Why does a floating input make a CMOS gate waste power?

A floating input hovers near the threshold voltage, leaving both the pull-up and pull-down partly on. That creates a direct path from power to ground, the very thing CMOS avoids, so the gate leaks current continuously and runs hot. Every input must be driven to a firm 0 or 1.

With the switches, networks, and power all understood, it is time to build real gates. Next: wire the inverter, transistor by transistor.

Every lesson here builds toward one thing: a working CPU, from the transistor up.

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Builds towardTransistor count and sizing