The transmission gate
An NMOS and PMOS in parallel that pass any value
A transmission gate is an NMOS and a PMOS wired in parallel and driven by complementary control signals, so that when enabled it passes both a strong 0 (through the NMOS) and a strong 1 (through the PMOS) in either direction, and when disabled it presents a high-impedance open switch.
Build it in the lab →So far every gate has *driven* its output from the rails. Sometimes, though, you just want a controllable switch that passes a signal through unchanged, the way the mechanical switches in logic as switches did. A single transistor cannot do it well: from NMOS you know a lone NMOS passes only a weak
1, and from PMOS a lone PMOS passes only a weak 0. The transmission gate fixes this by using both at once.Two transistors, opposite controls
Wire an NMOS and a PMOS in parallel: tie their two channel terminals together at the input side, and their other two together at the output side. Now drive them with complementary control signals. Call the control
EN: the NMOS gate gets EN, and the PMOS gate gets NOT EN (its complement, from an inverter). Both transistors therefore turn on together and turn off together.- **Enabled (
EN = 1, so PMOS gate= 0).** Both transistors conduct. Passing a0, the NMOS carries it at full strength (its strong side). Passing a1, the PMOS carries it at full strength (its strong side). Between them they deliver a strong 0 and a strong 1, so any value passes cleanly, and it passes in either direction. - **Disabled (
EN = 0, so PMOS gate= 1). Both transistors are off. The path is broken and the output side is left high-impedance** (Z): the transmission gate electrically lets go of the wire.
The trick is teamwork on strong sides. Wherever the NMOS is weak (passing a
1), the PMOS is strong, and wherever the PMOS is weak (passing a 0), the NMOS is strong. In parallel, the stronger one always wins, so the pair passes both logic values at full strength. That is why a transmission gate needs *both* transistor types, just like a full CMOS gate does, but for passing a signal rather than driving one.Pass-transistor logic
Using transmission gates (and sometimes lone transistors) to *route* signals rather than compute them from the rails is called pass-transistor logic. It can build some functions with strikingly few transistors: a 2-to-1 multiplexer, for instance, is just two transmission gates, one passing input
X when the select is 0 and the other passing input Y when the select is 1. Transmission gates are also how the storage loop of a D latch and flip-flop is opened and closed.A transmission gate passes a signal, it does not restore it. Unlike a full CMOS gate (which re-drives the output from
VCC/GND), a transmission gate offers no gain: the value that comes out is whatever drove the input, minus a little voltage drop and slowed by the gate's resistance. Chain several in a row and the signal weakens and slows. So pass-transistor logic is usually punctuated with a proper inverter or buffer every so often to restore the level. And because it can output Z when disabled, never leave a transmission-gate output as the only thing on a node unless a Z there is intended.A transmission gate is closely related to the tri-state buffer you meet later. Both can electrically disconnect (
Z) on command. The difference: a tri-state buffer is a driver (it re-creates a strong output from the rails and points one way), while a transmission gate is a bidirectional pass switch (it forwards whatever is on either side). Use a tri-state buffer to drive a shared bus; use a transmission gate to route or steer a signal.Try it
Why does a transmission gate use both an NMOS and a PMOS, when a single NMOS can already act as a switch? What goes wrong with the lone NMOS?
Answer
Build it in the lab ↗A lone NMOS passes a strong
0 but only a weak 1 (it cuts off about a threshold below the supply), so a 1 routed through it comes out degraded. Adding a parallel PMOS covers exactly that weak spot: the PMOS passes a strong 1. Together they pass both values at full strength. The complementary control (EN on the NMOS, NOT EN on the PMOS) makes them switch on and off as one.Frequently asked
What is a transmission gate?
A transmission gate is an NMOS and a PMOS wired in parallel and controlled by complementary signals. When enabled, both conduct and pass a full-strength
0 and 1 in either direction; when disabled, both turn off and the output goes high-impedance (Z). It is a clean bidirectional switch for routing signals.Why does a transmission gate need both an NMOS and a PMOS?
Because a lone NMOS passes only a weak
1 and a lone PMOS passes only a weak 0. Put in parallel, each covers the other's weak value, so the pair passes both a strong 0 and a strong 1.What is pass-transistor logic?
Pass-transistor logic builds functions by using transistors and transmission gates to route or steer signals rather than to drive outputs from the power rails. It can be very compact (a 2-to-1 multiplexer is two transmission gates), but it does not restore signal strength, so it is usually interspersed with buffers.
What is the difference between a transmission gate and a tri-state buffer?
Both can disconnect (
Z) on command. A transmission gate is a bidirectional pass switch that forwards whatever signal is on either side without restoring it; a tri-state buffer is a one-directional driver that re-creates a strong output from the rails. Use a tri-state buffer to drive a shared bus and a transmission gate to route a signal.Transmission gates unlock a compact build of the one gate that resists series-parallel design. Next: XOR at the transistor level.
You've got the theory. Now build it from scratch and watch it work.
Build it in the lab →Builds towardXOR at the transistor level