Complementary CMOS
Why gates use both NMOS and PMOS
Complementary CMOS builds a logic gate from a PMOS pull-up network to power and a complementary NMOS pull-down network to ground, with exactly one network conducting for any input so the output is always driven cleanly to 0 or 1.
Build it in the lab →Recall the two switches from the transistor: NMOS closes on a gate
1, PMOS closes on a gate 0. And recall from signals that a wire driven by nothing floats to Z, while a wire driven two ways at once shorts to X. This lesson combines those facts into the arrangement that gives a clean 0 or 1 every time. That arrangement is CMOS.The static CMOS skeleton
Every gate you will build follows the same two-network pattern. A pull-up network made of PMOS transistors can connect the output to
VCC (drive it to 1). A pull-down network made of NMOS transistors can connect the output to GND (drive it to 0). The two networks are always exact complements of each other: whenever one is conducting, the other is not.Because the networks are complementary, exactly one is closed at any instant. The output is therefore always actively driven to
1 or 0. It can never float to Z or short to X in a correctly built gate. That is the whole reason CMOS uses *both* transistor types instead of one.A familiar picture: a CMOS gate is a single-pole double-throw switch, the changeover switch on a model railway. The output is the moving contact; it is always thrown either up to the
VCC rail (through the pull-up) or down to the GND rail (through the pull-down), never stuck between them and never touching both rails at once. The inputs just decide which way it throws.The inverter: the simplest complementary pair
The NOT gate (inverter) uses one PMOS and one NMOS, both controlled by the same input
A. When A is 0, the PMOS closes and pulls F up to 1, while the NMOS is open. When A is 1, the NMOS closes and pulls F down to 0, while the PMOS is open. The two transistors hand off cleanly, with no instant where both conduct (a short) or neither conducts (a float).VCC, one NMOS pulling down to GND, the same input A driving both. Open it in the lab and toggle A: exactly one transistor lights up each time.| A | F |
|---|---|
| 0 | 1 |
| 1 | 0 |
A is 0 the PMOS is on, so F is 1. When A is 1 the NMOS is on, so F is 0.The buffer: two inverters in a row
Invert a signal twice and you are back where you started, so two inverters in series make a buffer (also called a driver): its output simply copies its input,
0 stays 0 and 1 stays 1. That sounds pointless until you remember what each inverter actually does. Every inverter re-drives its output straight from the VCC and GND rails through fresh transistors, so a buffer hands you the *same* logic value on a strong, clean drive. Reach for one when a signal has to cross a long wire or fan out to many gates and needs restoring, or when you want to drive a heavy load without letting it sag the original signal.| A | F |
|---|---|
| 0 | 0 |
| 1 | 1 |
Conduction rules to remember
- NMOS conducts when its gate is
1. (N for eNables-on-1.) - PMOS conducts when its gate is
0. The bubble on its gate is the reminder of that inversion. - To pull the output HIGH: find the input combinations that turn on a PMOS path to
VCC. - To pull the output LOW: find the input combinations that turn on an NMOS path to
GND. - Design the two networks so those two sets of combinations are complements. Then the output is always driven, and never both at once.
You can verify any gate by hand: for each input row, trace both networks. Exactly one should form a complete conducting path from the output to power or ground. If both conduct you have a short (
X); if neither does, the output floats (Z).Check yourself
In the inverter,
A = 1. Which transistor conducts, the PMOS or the NMOS? Is F connected to VCC or GND, and what value does it read?Answer
With
A = 1 the NMOS conducts (its gate sees 1) and the PMOS is off (its gate sees 1, and a PMOS needs 0). So F is connected to GND and reads 0. The output is the opposite of the input, which is exactly what an inverter does.How many inputs can one gate have?
Nothing limits a gate to two inputs. A 3-input, 4-input, or wider
AND or OR is perfectly normal: to add an input you add one more transistor to a network (one more in series inside a wider NAND, one more in parallel inside a wider NOR). But there is a practical ceiling. Each transistor you stack in series adds its own resistance and drops a little more voltage across the chain, so the gate switches more slowly and drives more weakly. Past about four inputs the slowdown is bad enough that designers stop widening a single gate and cascade smaller ones instead. To build an 8-input AND, for example, feed two 4-input AND gates into one 2-input AND, since AND(a..h) = AND( AND(a,b,c,d), AND(e,f,g,h) ). The logic is identical and every gate stays inside the safe fan-in limit.AND, OR, NAND, and NOR widen gracefully: add an input, add a transistor, then cascade once you pass the ~4-input limit. XOR and XNOR do not widen this way. Their output flips on every single input change (a wide XOR is really a parity check, 1 when an odd number of inputs are 1), and no simple series-or-parallel network captures that. So a multi-input XOR is always built as a chain of 2-input XOR gates, never as one wide gate. Do not reach for a 3-input XOR; there is no clean single-gate version.Aside: those cascades add up fast. In 1965, Intel co-founder Gordon Moore observed that the number of transistors on a chip was doubling about every year (a rate he later revised to about every two years), a trend named Moore's law, and it is why a modern processor packs billions of the tiny switches from the transistor lesson onto one sliver of silicon.
This skeleton never changes, only the wiring inside the two networks does. The next lesson, designing gates from truth tables, turns that wiring into a recipe you can run on any gate you will ever need, all the way up to the adders and registers of your CPU.
Spot the fault
A1pull-up PMOS1pull-down NMOS1FX
Look at F
Short (X)
Both networks are conducting at once: the PMOS ties
F to VCC while the NMOS ties it to GND, so the output is driven high and low simultaneously and reads X, a dead short. In a correct CMOS gate the two networks are complements, so exactly one conducts per input.Frequently asked
What is complementary CMOS?
Complementary CMOS builds a logic gate from a PMOS pull-up network to
VCC and a complementary NMOS pull-down network to GND. The two networks are exact complements, so exactly one conducts for any input and the output is always driven cleanly to 0 or 1.Why is CMOS complementary, and why use both NMOS and PMOS?
Because the pull-up and pull-down networks are complements, exactly one is closed at any instant, so the output is always actively driven and can never float to
Z or short to X in a correctly built gate. A single transistor type could not guarantee that: you need a PMOS (closes on 0) to pull HIGH and an NMOS (closes on 1) to pull LOW.How does a CMOS inverter (NOT gate) work?
A NOT gate uses one PMOS and one NMOS, both driven by the same input
A. When A is 0 the PMOS closes and pulls F up to 1 (the NMOS is open); when A is 1 the NMOS closes and pulls F down to 0 (the PMOS is open). The two transistors hand off cleanly, with no instant where both conduct or neither does.How can you verify a CMOS gate by hand?
For each input row, trace both networks: exactly one should form a complete conducting path from the output to
VCC or GND. If both conduct you have a short (X); if neither does, the output floats (Z).What is a buffer (driver) gate?
A buffer, or driver, is a non-inverting gate whose output copies its input (
0 stays 0, 1 stays 1). It is two inverters in series, so it changes nothing logically but re-drives the signal straight from the VCC and GND rails, giving a strong clean copy that can cross a long wire or fan out to many gates.How many inputs can a logic gate have?
AND, OR, NAND, and NOR can take several inputs, but stacking transistors in series slows the gate and weakens its drive, so the practical limit is about four inputs per gate; wider functions are built by cascading smaller gates (an 8-input AND is two 4-input AND gates feeding a 2-input AND). XOR and XNOR do not widen past two inputs at all and must be chained instead.You've got the theory. Now build it from scratch and watch it work.
Build it in the lab →