The complementary pair
Why exactly one network is ever on
A complementary CMOS gate joins a PMOS pull-up network and its dual NMOS pull-down network at a shared output, so that for every input combination exactly one network conducts, driving the output to a full-rail 0 or 1 with no floating and no short.
Build it in the lab →You have built both halves: an NMOS pull-down that drives the output to
0, and its dual PMOS pull-up that drives it to 1. This lesson joins them at a single output node and shows the payoff, the property that makes the whole scheme work. This is the same complementary CMOS skeleton from that lesson; here we prove why it never fails.Join the two networks at one output
Take the pull-up (PMOS, from
VCC down to the output) and the pull-down (NMOS, from the output down to GND) and wire their meeting point together. That shared node is the gate's output F. Every input drives one PMOS gate up top and one NMOS gate down below. The output is 1 when the pull-up conducts and 0 when the pull-down conducts. The only question that matters is: for a given input, which network is on?Exactly one, always
Because the pull-up is the exact dual of the pull-down, and the two transistor types conduct on opposite gate values, the two networks are logical complements. Whenever the pull-down forms a complete path to
GND, the pull-up is guaranteed broken, and whenever the pull-up forms a complete path to VCC, the pull-down is guaranteed broken. There is no input for which both conduct, and none for which neither conducts.- Both on would short
VCCstraight toGNDthrough the output, wasting power and leaving the output at an indeterminateX. The dual construction rules this out. - Neither on would leave the output driven by nothing, floating to
Z. The dual construction rules this out too. - Exactly one on is what always happens: the output is connected to one rail through a solid path, so it is a clean, actively driven logic value.
This is the entire reason CMOS uses *both* transistor types. One kind alone could pull only one way (and only weakly the other way). The complementary pair covers both jobs: the NMOS pull-down delivers a strong
0, the PMOS pull-up delivers a strong 1, and the dual topology guarantees exactly one is ever active. Full rails, no fights.The output is restored, not just passed
A subtle but important consequence: a CMOS gate does not *forward* its input signal, it re-creates the output straight from the
VCC and GND rails. However weak or noisy the input was (as long as it was clearly a 0 or a 1), the output is a fresh full-strength level driven by the rails through low-resistance transistors. That is why you can chain millions of gates in series without the signal decaying: every gate cleans it back up. A transmission gate, by contrast, only passes a signal through and does not restore it, which is a key difference you will meet later.A. Toggle A in the lab and watch exactly one transistor conduct each time, driving F to a full 1 or 0.Spot the fault
A1pull-up PMOSonpull-down NMOSonFX
Look at F
Short (X)
Both networks are conducting at once, tying
F to VCC and GND simultaneously, so it reads X and a large current flows straight through. In a correct complementary gate the pull-up is the exact dual of the pull-down, so exactly one network conducts per input and this short can never occur. A short like this usually means the two networks are not true duals.Check yourself
In a correctly built CMOS gate, is there any input combination for which the output floats to
Z? Explain in terms of the two networks.Answer
No. The pull-up and pull-down are exact duals, so they are logical complements: on every input row exactly one of them conducts. Whenever the pull-down is open, the pull-up is closed (driving
1), and vice versa. The output is therefore always connected to one rail through a conducting path, so it never floats. A floating output would mean the networks are not proper duals (a design bug).Frequently asked
Why is a CMOS gate called complementary?
Because its two networks are complements: a PMOS pull-up and an NMOS pull-down wired as exact duals. For every input combination exactly one of them conducts, so the output is always driven to a full
1 or 0, never floating and never shorted.Can both the pull-up and pull-down of a CMOS gate be on at once?
In a correctly designed gate, no. The dual construction guarantees the two networks are logical complements, so they never conduct on the same input. If both did conduct it would short
VCC to GND and leave the output at an indeterminate X, which signals a design error.Does a CMOS gate restore the signal?
Yes. A CMOS gate re-creates its output directly from the
VCC and GND rails through low-resistance transistors, rather than passing the input signal along. So the output is a fresh, full-strength logic level, which is why you can chain many gates without the signal decaying.Because exactly one network is on in steady state, there is no path from
VCC to GND, which has a striking consequence for power. That is the next lesson: why CMOS sips power.You've got the theory. Now build it from scratch and watch it work.
Build it in the lab →