The clock and sequential logic

Q: What is a clock signal in digital logic?

A clock is a signal that switches steadily between 0 and 1 at a fixed rate, 0,1,0,1,..., to pace a circuit. It carries no data; its only job is to tell every memory element *when* to update. The number of cycles per second is its frequency (a 3 GHz CPU clock ticks three billion times a second).

Q: What is the difference between combinational and sequential logic?

Combinational logic has outputs that depend only on the present inputs, so the same inputs always give the same output (every gate, the adder, a multiplexer). Sequential logic has outputs that also depend on stored state, so the same inputs can give different outputs depending on history (latches, flip-flops, registers, counters). The difference is memory.

Q: What is a clock edge?

A clock edge is the instant the clock changes value: the rising edge is the 0-to-1 transition and the falling edge is the 1-to-0 transition. Edge-triggered memory elements (like a D flip-flop) update their stored value at one edge per cycle and ignore their inputs the rest of the time.

Q: Why do all the parts of a CPU share one clock?

So they update in lockstep. Tying every memory element to one clock makes the design synchronous: nothing changes between edges, values just settle through the logic, and on the edge every storage element captures its input at once. This makes the machine predictable, and slowing or speeding the clock changes only how fast it runs, not what it computes.

The heartbeat that lets a circuit remember

6 min read

A clock is a signal that switches steadily between 0 and 1 to pace a circuit, and sequential logic is logic whose outputs depend on stored state, not just the present inputs. The clock tells every memory element exactly when to update so the whole circuit changes in lockstep.

Builds onSignals: 0, 1, Z, X Truth tables

This is the first page of the Memory group, and it teaches the one idea every later memory and processor lesson leans on: the clock. There is no circuit to build here, just two concepts to pin down (the clock signal and what *sequential* means), so the latch, flip-flop, register, counter, and CPU ahead all have firm ground to stand on.

Look back at everything you have built so far: gates, the half adder, the full adder. They all share one property. The output is a pure function of the inputs *right now*: change the inputs and the output follows, and the instant you remove the inputs the answer is gone. Logic like that is called combinational. A truth table describes it completely, because the present inputs are the whole story.

Combinational vs sequential

A computer cannot be only combinational, because it has to remember: hold a result while it computes the next one, keep a running total, know which instruction comes next. Logic whose output depends on what happened before, not just the inputs at this moment, is called sequential. The difference is memory.

Combinational: output depends only on the present inputs. Same inputs always give the same output. Examples: every gate and the adder you have built (and the multiplexers and decoders coming up).
Sequential: output depends on present inputs and stored history (the circuit's state). The same inputs can give different outputs depending on what came before. Examples: every latch, flip-flop, register, and counter in the lessons ahead.

The litmus test: if a circuit can give two different outputs for the same inputs, depending on its past, it is sequential, and it must be storing state somewhere. The very next lesson, the SR latch, is the simplest circuit that does exactly that. A truth table is no longer enough to describe it; you need to know its history too.

What a clock is

Once a circuit stores state, a new question appears: when should it update that state? If thousands of memory elements each updated whenever their inputs happened to change, the timing would be chaos. The answer is to give them all one shared timing signal, the clock: a single wire that marches steadily between 0 and 1 forever, 0,1,0,1,..., at a fixed rate. It carries no data. Its only job is to say *now*.

A clock has a few standard terms worth knowing, because every later lesson uses them:

Period: the time for one full 0-then-1 cycle. Frequency is how many cycles happen per second (a 3 GHz CPU clock ticks three billion times a second).
Rising edge: the instant the clock goes from 0 to 1. Falling edge: the instant it goes 1 to 0. The *edges* are the moments things happen.
Level: whether the clock is currently 0 (low) or 1 (high). Some elements care about the level, others only about the edge.

An analogy: a clock is a metronome (or a drummer setting the beat). It plays no melody, it just clicks at a steady tempo, and every musician changes notes together on the beat. In a chip, the memory elements are the musicians: on each clock edge they all update at once, so the machine moves in lockstep instead of every part drifting on its own.

Why one shared beat matters

Tying every memory element to one clock is what makes a design synchronous: nothing changes between edges, values just settle through the combinational logic, and then on the edge every storage element captures its input simultaneously. Slow the clock down and the machine runs in slow motion but computes the *identical* result; speed it up and it runs faster, up to the point where the combinational logic can no longer settle in one period. The clock sets the pace; the logic does the work.

A clock is not an input you compute with, and a faster clock does not change *what* a circuit calculates, only how quickly. A common beginner mistake is to treat the clock like a data signal or to expect the output to be 'more correct' at a higher frequency. The clock only decides when state updates; the logic between edges decides what that update is. Push the clock too fast and the logic simply will not have settled in time, which corrupts the result rather than improving it.

Check yourself

A circuit takes inputs A and B. With A = 1, B = 0 you sometimes read output 1 and other times read output 0, depending on what you did earlier. Is this circuit combinational or sequential? What must it contain?

You now have the vocabulary for the entire Memory and Processor sections. Combinational logic computes; sequential logic remembers; and the clock is the shared heartbeat that tells the sequential parts when to act. Next you build the first sequential circuit of all, the SR latch, using nothing but feedback, and then you give it a clock so it updates only when you say so.

Spot the fault

in1NOT out~

Look at NOT out

Oscillation (~)

An inverter whose output feeds straight back into its own input has no stable value: each pass flips it, so it never settles and the simulator marks it ~ (oscillating). Holding a value needs a clocked storage element to capture state between edges, not raw combinational feedback.

Frequently asked

What is a clock signal in digital logic?

A clock is a signal that switches steadily between 0 and 1 at a fixed rate, 0,1,0,1,..., to pace a circuit. It carries no data; its only job is to tell every memory element *when* to update. The number of cycles per second is its frequency (a 3 GHz CPU clock ticks three billion times a second).

What is the difference between combinational and sequential logic?

Combinational logic has outputs that depend only on the present inputs, so the same inputs always give the same output (every gate, the adder, a multiplexer). Sequential logic has outputs that also depend on stored state, so the same inputs can give different outputs depending on history (latches, flip-flops, registers, counters). The difference is memory.

What is a clock edge?

A clock edge is the instant the clock changes value: the rising edge is the 0-to-1 transition and the falling edge is the 1-to-0 transition. Edge-triggered memory elements (like a D flip-flop) update their stored value at one edge per cycle and ignore their inputs the rest of the time.

Why do all the parts of a CPU share one clock?

So they update in lockstep. Tying every memory element to one clock makes the design synchronous: nothing changes between edges, values just settle through the logic, and on the edge every storage element captures its input at once. This makes the machine predictable, and slowing or speeding the clock changes only how fast it runs, not what it computes.

Every lesson here builds toward one thing: a working CPU, from the transistor up.

Open the free lab →

Builds towardTwo kinds of circuit Shift registers Timing: delay and the clock speed limit Finite state machines