Flip-flops and latches cheat sheet
The memory elements of digital logic at a glance: SR latch, D latch, D flip-flop, JK, and T, each with its characteristic table, equation, and how it is built.
A latch is level-sensitive (it is transparent while its enable is active), while a flip-flop is edge-triggered (it samples its inputs only at the clock edge). Both store one bit by feeding their output back into their input; the clocking is what differs. Q is the current state and Q+ (Q next) is the state after the trigger.
At a glance
| Element | What it does | Trigger | Inputs |
|---|---|---|---|
| SR latch | Set drives the stored bit to 1, Reset to 0; with both inputs low it holds its value. | Level (asynchronous) | S, R |
| D latch (gated) | While Enable is high the output follows D (transparent); when Enable drops it freezes the last value. | Level (enable) | D, E |
| D flip-flop | Samples D on the clock edge and holds it until the next edge. The workhorse register bit. | Edge (clock) | D, CLK |
| JK flip-flop | Like an SR flip-flop, but the forbidden J=K=1 case is redefined to toggle, so every input is legal. | Edge (clock) | J, K, CLK |
| T flip-flop | Toggles on every clock edge when T=1, and holds when T=0. The building block of counters. | Edge (clock) | T, CLK |
Each element in detail
SR latch
Q+ = S + R'·Q (with S·R = 0)| S | R | Q next |
|---|---|---|
| 0 | 0 | Q (hold) |
| 0 | 1 | 0 (reset) |
| 1 | 0 | 1 (set) |
| 1 | 1 | invalid |
A cross-coupled pair of NOR gates (or NAND, active-low). Each output feeds back into the other gate, and that loop is what stores the bit.
Full SR latch lesson →D latch (gated)
Q+ = E·D + E'·Q| E | D | Q next |
|---|---|---|
| 0 | x | Q (hold) |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
An SR latch with a gate: Enable ANDs D onto Set and D' onto Reset, so it can only change while enabled. Removes the SR invalid state.
Full D latch (gated) lesson →D flip-flop
Q+ = D| D | Q next |
|---|---|
| 0 | 0 |
| 1 | 1 |
Two D latches in series (master-slave) on opposite clock phases, so the output changes only at the instant the clock edges, never while the clock is steady.
Full D flip-flop lesson →JK flip-flop
Q+ = J·Q' + K'·Q| J | K | Q next |
|---|---|---|
| 0 | 0 | Q (hold) |
| 0 | 1 | 0 (reset) |
| 1 | 0 | 1 (set) |
| 1 | 1 | Q' (toggle) |
A D flip-flop (or SR) with feedback: J and K are combined with the current Q so that J=K=1 flips the state instead of being invalid.
Full JK flip-flop lesson →T flip-flop
Q+ = T XOR Q| T | Q next |
|---|---|
| 0 | Q (hold) |
| 1 | Q' (toggle) |
A JK flip-flop with J and K tied together (T), or a D flip-flop whose D is wired to Q XOR T. Chain them and each stage halves the frequency: a ripple counter.
Full T flip-flop lesson →