Shift registers

Q: What is a shift register used for?

Three main jobs: serial-to-parallel conversion (clock bits in one wire at a time, then read the whole word across the outputs), parallel-to-serial conversion (load a word, clock it out one bit at a time), and fast arithmetic (shifting a binary number left multiplies by 2, shifting right divides by 2).

Marching a bit along a chain

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A shift register is a chain of flip-flops in which each flip-flop's output feeds the next one's input, so on every clock edge every stored bit moves one position along the chain. It shifts data one step per clock and converts between serial and parallel form.

Builds onD flip-flop Register bit The clock and sequential logic

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A register bit holds one value in place, and lining several up (sharing a clock) gives a register that holds a whole word steady. A shift register does something different: it makes the stored bits move. Wire a row of flip-flops so each one's output Q feeds the *next* one's input D, share one clock across them all, and on every clock edge every bit steps one position along the chain. It is the standard way to move data one bit at a time and to walk a pattern through hardware.

Flip-flops in a chain

Take four D flip-flops and connect them in a line: the serial input IN drives the first flip-flop's D, the first flip-flop's Q0 drives the second's D, Q1 drives the third's D, and so on. Every flip-flop shares the same clock line. Because a flip-flop captures its D only at the rising edge, on each edge stage 1 grabs whatever stage 0 held, stage 2 grabs stage 1, all at the same instant. The whole row shifts right by one.

on each rising edge: Q0 <- IN, Q1 <- Q0, Q2 <- Q1, Q3 <- Q2

Every stage captures the old value of the stage before it, not the new one, because all the flip-flops sample at the *same* edge. That simultaneity is exactly why edge-triggered flip-flops are used here and not transparent latches: if the cells were transparent, a single bit could race down the entire chain in one clock instead of advancing one step. The clock edge freezes each hand-off cleanly.

Watching a bit walk the chain

Feed a single 1 into IN for one clock, then hold IN = 0. The 1 enters stage 0, then marches Q0, Q1, Q2, Q3 on successive edges, one step per clock, until it falls off the end:

Start with the chain cleared and IN = 1. After edge 1: Q0 Q1 Q2 Q3 = 1 0 0 0.
Drop IN = 0. After edge 2: 0 1 0 0. The 1 moved from stage 0 to stage 1.
After edge 3: 0 0 1 0. After edge 4: 0 0 0 1. The 1 keeps walking right.
After edge 5: 0 0 0 0. The bit has shifted off the end of the chain.

A 4-bit shift register: four D flip-flops chained Q0 -> D1 -> Q1 -> D2 ..., all on one clock. A bit on IN walks Q0 to Q1 to Q2 to Q3, one step per clock edge. Before the first clock the outputs read Z; open it in the lab, set IN = 1 and pulse the clock once, then set IN = 0 and keep clocking to watch the single 1 march along.

Direction and timing are the two easy mistakes. Wire Q of a later stage back into an earlier stage's D and the data shifts the *other* way (or loops), which is rarely what you meant; keep the chain flowing one direction. And remember each edge advances the pattern by exactly one position: to push an 8-bit byte in serially you need eight clock edges, not one.

Why shift registers are everywhere

Shifting is useful in several ways at once. Serial to parallel: clock 8 bits in one wire at a time, and after 8 edges the byte sits across Q0-Q7, readable all at once (this is how a chip receives data over a single wire). Parallel to serial: load a byte into all stages, then clock it out one bit at a time onto one wire. And shifting a binary number left multiplies it by 2, shifting right divides by 2, which is how a CPU does fast multiply-and-divide-by-powers-of-two.

Try it

A 4-bit shift register holds Q0 Q1 Q2 Q3 = 0 1 1 0 and IN = 1. What does it hold after the next clock edge? Why does each stage take the previous stage's *old* value?

Build it in the lab ↗

The universal shift register

So far each register does one job: an 8-bit register loads all its bits at once and holds them, while the chain above only shifts. A universal shift register does every job and lets you choose which one on each clock edge. The trick is to place a small chooser in front of every flip-flop's D. Recall the multiplexer: a 4-to-1 mux has four data inputs and a 2-bit select S1 S0, and it passes exactly the one input you pick. Give every flip-flop its own 4-to-1 mux, wire the same mode select S1 S0 to all of them, and feed each mux the four sensible sources for that stage.

S1 S0 = 0 0, hold: each mux passes the flip-flop's own Q back to its D, so the word is rewritten unchanged and nothing moves.
S1 S0 = 0 1, shift right: each mux passes the neighbour to its left, Q(i-1), so the word steps one place along the chain; the first stage Q0 has no left neighbour, so it takes a serial right-in bit.
S1 S0 = 1 0, shift left: each mux passes the neighbour to its right, Q(i+1), so the word steps the other way; the last stage Q3 has no right neighbour, so it takes a serial left-in bit.
S1 S0 = 1 1, parallel load: each mux passes an external input Pi, so all the flip-flops overwrite together in one edge, exactly like the parallel-load register.

Notice the neat part: the 2-bit mode is *literally* the mux select, so 00, 01, 10, 11 name the four behaviours directly. One shared select drives every bit, so the whole register always does a single mode per edge (you cannot hold some bits while shifting others). This one configurable part is the standard register a processor reaches for whenever a value must sometimes shift and sometimes load; the classic 74x194 chip is exactly this. For shifting a whole word by many places in a single combinational step instead of one place per clock, see the barrel shifter.

A worked example: the serial adder

Shift registers do more than move data around: chain one to an adder and you get arithmetic that trades chips for clock cycles. A serial adder adds two numbers one bit per clock, least-significant bit first, using a single full adder instead of one adder per bit. Put the two numbers in two shift registers, A and B, lined up so their low bits come out first. On each edge the low bit of A and the low bit of B meet at the full adder along with a carry bit held in one flip-flop. The adder makes a sum bit and a carry-out: the sum bit shifts into the result (often back into A, whose bits have already been used), and the carry-out is stored in the carry flip-flop to serve as the carry-in for the next, higher column.

Recall the full adder's rule for three input bits a, b, and carry-in c: the sum bit is a XOR b XOR c (a 1 when an odd number of the three are 1), and the carry-out is 1 when at least two of them are 1. The carry flip-flop just remembers that carry-out from one clock to the next. Add A = 0101 (five) and B = 0011 (three); the registers present their bits low end first, and the carry flip-flop starts cleared to 0 because nothing carries into the lowest column:

Clock	A bit	B bit	carry-in	sum bit	carry-out
1	1	1	0	0	1
2	0	1	1	0	1
3	1	0	1	0	1
4	0	0	1	1	0

Adding 0101 + 0011, one column per clock, least-significant bit first. The sum bits appear low bit first as 0, 0, 0, 1; written most-significant-bit on the left that is 1000. Five plus three is eight, and the final carry-out is 0, so the answer fits in four bits.

Clock 1, the lowest column: A bit 1, B bit 1, carry-in 0. Sum = 1 XOR 1 XOR 0 = 0; two inputs are 1, so carry-out = 1. The carry flip-flop stores 1.
Clock 2: A bit 0, B bit 1, carry-in 1 (the stored carry). Sum = 0 XOR 1 XOR 1 = 0, carry-out = 1 again.
Clock 3: A bit 1, B bit 0, carry-in 1. Sum = 1 XOR 0 XOR 1 = 0, carry-out = 1.
Clock 4, the top column: A bit 0, B bit 0, carry-in 1. Sum = 0 XOR 0 XOR 1 = 1, carry-out = 0. The carry is finally absorbed, and the four sum bits 1000 are the answer.

The serial adder is the classic area-versus-speed trade-off. A parallel adder wires one full adder per bit and produces the whole sum in a single clock, but it costs n full adders for n bits. The serial adder reuses one full adder and one carry flip-flop for any width, so it is far smaller, but it needs n clock edges to finish. Wider numbers cost the serial design more time and the parallel design more silicon, and real hardware picks a point on that line: tiny, low-power parts lean serial, while fast processors pay for parallel.

Two things bite here. First, **clear the carry flip-flop to 0 before the lowest bit**, or a stale 1 left from a previous addition quietly adds one to the answer. Second, the numbers must arrive least-significant bit first: line the registers up the wrong way and the adder combines the wrong columns, so the carry flows in the wrong direction and the result is garbage. The scheme also assumes exactly one clock per bit, so an n-bit add is not finished until the n-th edge.

Try it

A serial adder is adding A = 0110 and B = 0011, least-significant bit first, with the carry flip-flop cleared to 0. Work through all four clocks: what sum bits come out, and what is the four-bit result?

One variation matters for the processor ahead: feed the last stage back into the first, and instead of falling off the end the single 1 cycles around the loop forever. That looped shift register is a ring counter, and it is exactly how the control unit will produce its repeating step sequence T0, T1, T2, T3 (you will build it as a state machine). Next, though, the limits of clocking: how fast can the edges actually come? That is timing.

Frequently asked

What is a shift register?

A shift register is a chain of flip-flops where each one's output feeds the next one's input, all sharing a clock. On every clock edge every stored bit moves one position along the chain, so it shifts data one step per clock.

What is a shift register used for?

Three main jobs: serial-to-parallel conversion (clock bits in one wire at a time, then read the whole word across the outputs), parallel-to-serial conversion (load a word, clock it out one bit at a time), and fast arithmetic (shifting a binary number left multiplies by 2, shifting right divides by 2).

Why does a shift register use flip-flops instead of latches?

Because edge-triggered flip-flops all sample at the *same* instant, so each stage captures the old value of the stage before it and the pattern advances exactly one position per clock. Transparent latches would let a bit race down the whole chain in a single clock, which defeats the point of shifting one step at a time.

What is the difference between a shift register and a normal register?

An 8-bit register loads all its bits in parallel and holds them in place. A shift register instead moves its bits one position along a chain on each clock edge. A ring counter is a shift register wired in a loop so the pattern cycles instead of falling off the end.

What is a universal shift register?

A universal shift register can hold, shift right, shift left, or parallel-load its bits, chosen by a 2-bit mode select. It works by putting a 4-to-1 multiplexer in front of every flip-flop, all sharing the same select, so the mode picks each flip-flop's next value: its own output (hold), a neighbour (shift), or an external input (load).

What is a serial adder and how is it different from a parallel adder?

A serial adder adds two numbers one bit per clock, least-significant bit first, using a single full adder and a carry flip-flop that hands each column's carry to the next. A parallel adder instead uses one full adder per bit and produces the whole sum in a single clock. The serial version is much smaller but takes one clock per bit; the parallel version is faster but costs more hardware.

You've got the theory. Now build it from scratch and watch it work.

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