OR
NOR, then inverted
An OR gate outputs 1 when at least one of its inputs is 1. In CMOS it is built as a NOR gate followed by an inverter, mirroring how AND is built from NAND.
Build it in the lab →If you built AND from NAND, you already know this lesson; just swap the parts. OR is NOR with a NOT on its output, exactly as AND was NAND with a NOT. Same recipe, dual gate.
OR produces
1 whenever at least one input is 1, and 0 only when both are 0. Like AND it is non-inverting, so in CMOS you build it from its cheaper inverting cousin: NOR, then NOT.| A | B | F |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
0. Any high input is enough to drive the output high.F = A ∨ B
NOR then NOT: the same recipe as AND
NOR gives you
NOT (A OR B). Feeding that into NOT cancels the outer inversion: NOT (NOT (A OR B)) is just A OR B. Two stages, two saved parts.- Place your saved NOR. Connect
AandBto its inputs; its output isNOT (A OR B), high only when both inputs are0. - Place your saved NOT. Feed the NOR output into it.
- The result simplifies to
A OR B. - Label the final output
F. OR built from two inverting stages.
There is a second route that avoids NOR entirely:
F = (NOT A) NAND (NOT B). De Morgan's law shows it is the same function (NOT(A' · B') = A + B). The NOR-then-NOT path just uses fewer parts here, because NOR is already one unit in your library.Try it
Build OR as NOR -> NOT. For inputs
A = 0, B = 0, trace the value through the NOR and then the NOT. Why is this the only row where OR is 0?Answer
With
A = B = 0, the NOR outputs 1 (NOR is high only when both inputs are 0), and the NOT inverts it to 0, the correct 0 OR 0 = 0. Every other row has at least one 1, making the NOR 0, which the NOT turns into 1. So only the all-0 row gives OR a 0.Notice the symmetry: AND = NAND + NOT, OR = NOR + NOT. Inverting gates are cheap in CMOS, so you build them first and cancel the inversion. That habit scales straight up to the larger blocks ahead.
With OR saved you now hold all four basic gates as reusable parts (AND, OR, NAND, NOR) plus NOT. The next group spends them on arithmetic, where OR will merge the two carry signals inside a full adder, the heart of your CPU's adder.
Frequently asked
What is an OR gate?
An OR gate outputs
1 when at least one of its inputs is 1, and 0 only when every input is 0.How is an OR gate built in CMOS?
As a NOR gate followed by a NOT, mirroring how AND is built from NAND:
NOT (A NOR B) = A OR B. Inverting gates are cheaper in CMOS, so you build NOR first and cancel the inversion.What is the difference between OR and XOR?
They agree everywhere except when both inputs are
1: 1 OR 1 = 1, but 1 XOR 1 = 0. OR is "one or the other, or both"; XOR is "one or the other, but not both."You've got the theory. Now build it from scratch and watch it work.
Build it in the lab →