Hazards and glitches

Q: How do you fix a static-1 hazard?

Add the redundant consensus term that bridges the two non-overlapping prime-implicant groups the input change crosses between. On a Karnaugh map, draw an extra group that covers both cells the single-bit change moves between; its product term keeps the output 1 through the transition. The term is logically redundant (it changes no truth-table row) but holds the output steady against the timing gap.

Q: How do you find a hazard on a Karnaugh map?

Look for two adjacent 1 cells that differ in a single input bit but are covered by different prime-implicant groups that do not overlap. A one-bit input change between those two cells hops from one group to the other, and the gap between one term switching off and the other switching on is where the static-1 glitch appears.

Q: What is the difference between a logic hazard and a function hazard?

A logic hazard is a glitch from unequal delays on a single input change, and it is removable by adding consensus terms. A function hazard occurs when two or more inputs change at once and the function's own values along that path require a transition; it cannot be removed by adding terms, so the only defense is to avoid changing multiple inputs simultaneously.

The momentary wrong answer a correct circuit can still produce

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A hazard is a momentary wrong output (a glitch) that a logically correct combinational circuit can produce during a single input change because its gates have unequal delays; a static-1 hazard in an AND-OR circuit is removed by adding the redundant consensus term that bridges the two adjacent prime-implicant groups the input change crosses between.

Builds onKarnaugh maps Designing gates from truth tables

You can already turn a truth table into a minimal circuit with a Karnaugh map and realize it with the CMOS recipe. Those steps get the *logic* right. This lesson is about getting the *timing* right. Everything so far has treated gates as instant: change an input, read the new output. Real gates take time to switch, and different paths through a circuit take different amounts of time. That gap can make a perfectly correct circuit flash the wrong value for a few nanoseconds while one input changes, even though its truth table is exactly right. That momentary wrong answer is a hazard (the resulting blip on the wire is a glitch), and learning to spot and remove it is the last skill of combinational design.

This is invisible in our simulator (and that is the point). The lab settles every circuit with zero gate delay, so it only ever shows the correct steady-state value, never the glitch in between. Hazards are a property of *timing*, not of logic, so you have to reason about them on paper. This lesson teaches you to see a glitch the simulator cannot draw.

An analogy: the baton handoff

Picture two runners in a relay passing a baton. For the race to count, the baton must never touch the ground. If the first runner lets go a hair before the second has gripped it, there is a brief instant where nobody holds the baton and it drops, even though both runners did their part. A circuit's output can drop the same way: as the design hands responsibility for keeping the output 1 from one gate to another, a timing gap can leave the output momentarily held by *neither*, and it dips to 0. The fix, as you will see, is a third hand that grips the baton through the whole handoff.

Static hazards: a 1 that dips, a 0 that spikes

The two basic cases are named for the value that *should* hold steady:

Static-1 hazard: the output should stay 1 across an input change, but it momentarily dips to 0. This is the classic glitch of a two-level AND-OR (SOP) circuit, where keeping the output 1 is the job of the product terms.
Static-0 hazard: the output should stay 0, but it momentarily spikes to 1. This is the mirror case in a two-level OR-AND (POS) circuit, where the sum terms keep the output 0.

Both come from the same cause: one input reaching part of the circuit slightly before it reaches another part, usually because one path passes through an extra inverter (NOT gate) and the other does not. While the two copies of the signal briefly disagree, the output can take the wrong value.

Worked example: spotting a static-1 hazard on a K-map

Take F = A·B + A'·C, a minimal SOP with two product terms. Its truth table is 1 on rows 1, 3, 6, 7:

A	B	C	F
0	0	0	0
0	0	1	1
0	1	0	0
0	1	1	1
1	0	0	0
1	0	1	0
1	1	0	1
1	1	1	1

F = A·B + A'·C. The term A'·C covers rows 1 and 3 (where A=0, C=1); the term A·B covers rows 6 and 7 (where A=1, B=1). The two groups meet but do not overlap.

On the Karnaugh map (rows A, columns BC in Gray order 00, 01, 11, 10), the term A'C is the pair of 1s in the top row at columns 01 and 11; the term AB is the pair of 1s in the bottom row at columns 11 and 10. Now look at the column BC = 11: it holds m3 (top, A=0) and m7 (bottom, A=1), two adjacent 1 cells that differ in a single bit, A. But m3 is covered only by the A'C group and m7 only by the AB group, and those two groups do not overlap. That is the visual signature of a static-1 hazard: a one-bit input change hops from one prime-implicant group to a different, non-overlapping one.

Hold B = 1 and C = 1, and toggle A from 1 to 0. The output should stay 1 the whole time (both m7 and m3 are 1-rows).
With A = 1, the A·B term holds the output high. With A = 0, the A'·C term should take over (since A' is now 1).
But A' comes from an inverter, so it rises slightly *after* A falls. For that brief gap, A is already 0 (so A·B has switched off) while A' has not yet reached 1 (so A'·C has not switched on).
For those few nanoseconds neither product term is 1, the OR sees all-0 inputs, and F dips to 0: a glitch on a wire that should have been a steady 1.

The fix: add the consensus term

The cure is to give the output a term that stays 1 across the whole transition, a third hand on the baton. On the K-map, draw a redundant group that covers both m3 and m7, the cells the change moves between. That group is the column BC = 11, which is the term B·C. In algebra it is the consensus of A·B and A'·C: when two terms have one variable in opposite forms (A and A' here), their consensus is the AND of the leftover literals (B from one, C from the other), giving B·C. Add it:

hazardous: F

= A·B + A'·C hazard-free: F

= A·B + A'·C + B·C

The extra B·C term is logically redundant: it does not change a single row of the truth table (every row it covers was already 1). Its only job is timing. While A toggles with B = C = 1, the B·C term stays 1 the entire time and holds the output up through the handoff, so the OR never sees all-zeros and F never dips. The figure below is this hazard-free circuit:

The hazard-free cover F = A·B + A'·C + B·C: the two original product terms plus the redundant consensus term B·C (three ANDs into an OR). Open it in the lab and sweep all eight rows; its truth table is identical to A·B + A'·C (the B·C term changes no output), but in real hardware that term is what keeps F from glitching when A flips with B = C = 1.

Why bother, if the steady-state logic is already correct? Because some circuits sample the wire while it might be glitching. A glitch is harmless in synchronous, edge-triggered design (a flip-flop only looks at its input at the clock edge, long after the combinational logic has settled, so it never sees the dip). But a glitch is dangerous anywhere that reacts to a *level* rather than an edge: a level-sensitive latch, asynchronous logic, or any signal used directly as a clock, a register load-enable, a write-enable, or a reset. There a one-nanosecond spike can latch the wrong value or trigger an unintended write. Those signals need a hazard-free cover, the SOP with all its consensus terms included.

Dynamic, logic, and function hazards

Static hazards are not the only kind. A few distinctions complete the picture:

Dynamic hazard: during a single input change the output *should* switch once (0 to 1 or 1 to 0) but instead bounces several times (for example 0 -> 1 -> 0 -> 1) before settling. These arise in multilevel circuits (more than two gate levels) where a signal reaches the output along three or more paths of different delay. Flattening to a clean two-level hazard-free form avoids them.
Logic hazard: a glitch caused purely by unequal delays on a single input change. These are removable by adding consensus terms, which is everything above.
Function hazard: a glitch that happens when two or more inputs change at the same time and the function's own values along the path require a transition. These cannot be removed by adding terms, because the table itself demands the output move. The only defense is to not change multiple inputs simultaneously, which is one more reason synchronous design lets inputs settle before the clock edge.

Common mistakes. A glitch does not mean your logic is wrong: the steady-state truth table is correct, and the hazard is purely about timing. The consensus term you add is logically redundant, it never changes a single truth-table row, it only fills the timing gap, so do not expect it to alter the function. Match the hazard to the form: static-1 hazards live in AND-OR (SOP) circuits, static-0 hazards in OR-AND (POS) circuits. And do not try to delete a function hazard by adding terms: only logic hazards (single-input-change glitches) are removable; a function hazard (from two or more inputs changing at once) is baked into the table and must be avoided instead.

Try it

You have the SOP F = A·C' + B·C (two product terms). Around which input transition could a static-1 hazard occur, and what single redundant term removes it? (Hint: find the variable that appears in both terms in opposite forms.)

Hazards are why a real design rule reads "do not gate the clock with combinational logic" and why enables and resets get special, glitch-free treatment. In a fully synchronous circuit you can usually *ignore* combinational glitches, because the flip-flops only sample after everything has settled, and that tolerance is a big reason the synchronous, clocked style won. Speaking of which, the next group puts these settled gates to work on real arithmetic, starting with adding two bits in the half adder, and then the Memory group introduces the clock and the storage cells that make the sample-after-settling discipline possible.

Frequently asked

What is a hazard in a digital circuit?

A hazard is the potential for a momentary wrong output (a glitch) in a combinational circuit during a single input change, caused by unequal gate delays even though the steady-state logic is correct. A static-1 hazard is a 1 that briefly dips to 0; a static-0 hazard is a 0 that briefly spikes to 1; a dynamic hazard is an output that bounces several times before settling.

How do you fix a static-1 hazard?

Add the redundant consensus term that bridges the two non-overlapping prime-implicant groups the input change crosses between. On a Karnaugh map, draw an extra group that covers both cells the single-bit change moves between; its product term keeps the output 1 through the transition. The term is logically redundant (it changes no truth-table row) but holds the output steady against the timing gap.

How do you find a hazard on a Karnaugh map?

Look for two adjacent 1 cells that differ in a single input bit but are covered by different prime-implicant groups that do not overlap. A one-bit input change between those two cells hops from one group to the other, and the gap between one term switching off and the other switching on is where the static-1 glitch appears.

Why do hazards matter if the circuit is logically correct?

Because some logic samples the wire while it is still glitching. Synchronous, edge-triggered flip-flops only read their input at the clock edge, after the combinational logic has settled, so they tolerate glitches. But level-sensitive latches, asynchronous logic, and any signal used as a clock, load-enable, write-enable, or reset can be corrupted by a one-nanosecond spike, so those need a hazard-free cover.

What is the difference between a logic hazard and a function hazard?

A logic hazard is a glitch from unequal delays on a single input change, and it is removable by adding consensus terms. A function hazard occurs when two or more inputs change at once and the function's own values along that path require a transition; it cannot be removed by adding terms, so the only defense is to avoid changing multiple inputs simultaneously.

Every lesson here builds toward one thing: a working CPU, from the transistor up.

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