FPGAs and programmable logic
A blank chip that becomes your circuit
An FPGA (field-programmable gate array) is a chip full of generic logic blocks (configurable look-up tables plus flip-flops) and programmable wiring that you configure with a stored bit pattern, so the same silicon becomes whatever digital circuit you describe, with no custom fabrication.
You have designed circuits two ways: by hand, deriving the minimal gates from a truth table with a Karnaugh map, and in text, describing the behavior and letting synthesis work out the gates. Both end with a question this lesson answers: where do those gates physically come from? You could etch a custom chip for every design, but that is slow and expensive. The alternative is a programmable logic device: a generic chip, manufactured once with no particular function, that you configure to become your circuit. Instead of wiring fixed gates, you set a pattern of bits that makes a blank chip behave exactly like the logic you designed.
The simplest idea: a ROM is a truth table
Start with a ROM (read-only memory). A ROM stores one word at each address: put an address on its input lines and the stored word appears on its outputs. Now read that the right way. Feed your circuit's inputs in as the address, and store at each address the output your function should produce for those inputs. The ROM's contents are then literally the **output column of a truth table**: an
n-input, m-output combinational function is just a ROM with n address lines and m-bit words, holding 2^n entries. You do not build gates at all; you store the answers and look them up.| A | B | word |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
(A,B) storing the XOR function. The address is the input, the stored word is the output, so the ROM's contents ARE the truth table. This is the seed of the whole idea: configure storage, not wiring.A ROM lookup is brute force: it needs one stored entry for every input combination, so cost grows as
2^n. A 20-input function would need a million-entry table. That is why the cleverer devices below store minimized logic (the kind a Karnaugh map produces) rather than the full table, until the FPGA's look-up table brings the small-table idea back in a smarter package.PLA and PAL: sum-of-products in silicon
Your Karnaugh map work always ends in the same shape: a sum of products (SOP), a few AND terms ORed together, like
F = A'·B + A·B'. A PLA (programmable logic array) implements that shape directly in hardware. It has two planes of wires. The programmable AND plane forms product terms: each horizontal product line can be wired to any input or its complement, so one line becomes one AND term. The programmable OR plane then sums chosen product lines onto each output. Lay your minimized SOP onto it term by term and the function is built, no gates to place.F = A'·B + A·B' (one ∧-plane product line per term, summed by the ∨ plane)
A PAL (programmable array logic) is the cheaper, faster cousin: its AND plane is programmable but its OR plane is fixed, so each output sums a fixed number of product terms (commonly up to 7 or 8). You lose the ability to share an arbitrary set of product terms across outputs, but the simpler structure is faster and was historically much cheaper, which made PALs the workhorse of programmable logic for years.
This is why SOP minimization is not just a paper exercise. A PLA or PAL has a limited number of product-term lines, so the fewer AND terms your Karnaugh map leaves, the more likely the function fits, and product-term sharing (one product line feeding several outputs in a PLA) shrinks it further. Minimizing the logic and minimizing the silicon are the same job here.
CPLDs: many PAL blocks on one chip
A single PAL holds only a modest function. A CPLD (complex programmable logic device) packs many PAL-like blocks onto one chip and joins them with a central programmable interconnect that routes signals between blocks. Each block still works by product terms, so a CPLD has the PAL's strengths: configuration held in non-volatile memory (it works the instant it powers on, no external load needed) and predictable, uniform timing, because almost every path crosses the same interconnect once. CPLDs suit modest glue logic and control; they run out of room well before a processor.
The FPGA: a sea of look-up tables
An FPGA (field-programmable gate array) scales far beyond a CPLD by abandoning product terms for a different primitive: the look-up table (LUT). And here is the punchline of the whole lesson, a LUT is literally a tiny ROM, a truth table stored in SRAM. An
n-input LUT holds 2^n configuration bits, one per input combination; its inputs address those bits and the addressed bit is the output. Because every one of those 2^n bits is independently 0 or 1, an n-input LUT can be loaded to compute any function of n inputs at all. Real FPGAs use 4-input to 6-input LUTs as their atom of logic.Those LUTs do not float alone. An FPGA is a regular grid of configurable logic blocks (CLBs), each a LUT paired with a **flip-flop so the block can do combinational logic, registered logic, or both. Around and between them runs a mesh of programmable routing (switch boxes you configure to connect any block's output to any other block's input), plus dedicated hard blocks the fabric would be wasteful at: block RAM** for memory like the RAM you built, DSP slices (hard multiply-accumulate units) for arithmetic, and I/O blocks at the edges that connect to real pins. Configure the LUT contents, the flip-flop modes, and the routing switches, and the blank grid becomes your design.
Worked example: reprogramming one LUT
Take a 2-input LUT. It has four SRAM cells, addressed by
(A,B) as 00, 01, 10, 11. To make it an XOR gate, load the four cells with XOR's output column, 0, 1, 1, 0. The LUT now outputs 1 exactly when its inputs differ, an XOR, even though no XOR gate exists anywhere on the chip:| A | B | LUT bit |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
0,1,1,0, the XOR output column. The inputs (A,B) address the cell; the stored bit is the result.- The LUT is XOR purely because its four cells hold
0,1,1,0. Nothing else about the silicon mentions XOR. - Want an AND gate on the same physical LUT? Rewrite the four cells to AND's output column:
0,0,0,1(high only atA=1,B=1). - Want a NOR instead? Load
1,0,0,0. Want a constant1? Load1,1,1,1. The function the gate computes IS the bit pattern you store. - No re-wiring, no new chip: changing the four stored bits changes the gate. That is what 'programmable' means at the lowest level.
Look at what just happened: the same circuit element was a logic gate and a memory, and switching between functions was nothing but writing memory. That is the deep idea a LUT makes concrete, logic and memory are the same thing at the bottom. A truth table and a stored table are identical; an FPGA computes by remembering answers.
From your HDL to a configured chip
A LUT-and-routing fabric is useless without a tool to fill it in. You do not hand-place LUTs any more than you hand-place transistors; you write HDL and a tool chain (Xilinx Vivado, Intel Quartus) turns it into a configuration. The flow:
- Synthesis: read the HDL and work out the gates and flip-flops it implies (the step from the HDL lesson).
- Technology mapping: pack those gates into the chip's actual primitives, folding clusters of logic into 4-to-6-input LUTs and assigning flip-flops to CLBs.
- Place and route: choose which physical CLB each piece of logic lives in, then configure the routing switches to wire them together across the fabric.
- Bitstream generation: emit one big binary file (the bitstream) holding every LUT's contents, every flip-flop mode, and every routing-switch setting.
- Configuration: load the bitstream into the FPGA's SRAM, and the blank grid powers up as your circuit. (SRAM is volatile, so an FPGA reloads its bitstream from flash on every power-up.)
One step matters as much as the others: static timing analysis (STA). After place and route the tool knows the real delay of every wire and LUT, so it checks every path between flip-flops against the setup and hold limits from the timing lesson. If a path is too slow to meet setup at the target clock speed, timing does not close, and you must slow the clock, restructure the logic, or add pipeline stages. Only when STA passes is the bitstream trustworthy.
Common mistakes. An FPGA is not faster or denser than a custom chip: a reprogrammable LUT fabric pays for its flexibility in area and speed, so an ASIC (a standard-cell chip etched with photomasks in a factory) of the same design runs faster, smaller, and cheaper per unit, but only at high volume and with no field reconfiguration ever again. A wrong bitstream is a software fix; a wrong mask set is a multi-million-dollar respin. Also, an
n-input LUT does not mean n gates: it is one element that holds any n-input function, and synthesis packs whole gate clusters into each one. And do not expect a design to run just because synthesis succeeded, it must also close timing in STA at your clock speed.Why this matters: this is the rung where the circuits in this course become real hardware you can run. The transistor-level understanding you built tells you what each line of HDL becomes, and the FPGA tells you where it physically lives, in LUTs and flip-flops and routing on an actual chip in Vivado or Quartus. The LUT also closes a loop the whole course has been circling, that a truth table, a stored memory, and a logic function are three views of one thing.
Check yourself
A 3-input LUT sits inside an FPGA's logic block. How many SRAM configuration bits does it hold, and how many distinct 3-input logic functions can it be programmed to compute?
Answer
A 3-input LUT has one stored bit per input combination, so it holds
2^3 = 8 configuration bits (it is an 8-entry ROM addressed by the three inputs). Since each of those 8 bits is independently 0 or 1, the number of distinct bit patterns is 2^8 = 256, and each pattern is a different output column, so the LUT can be loaded to compute any of the 256 possible 3-input functions, the complete set. That universality is exactly why a grid of LUTs can become any circuit at all.Frequently asked
What is an FPGA?
An FPGA (field-programmable gate array) is a chip full of generic configurable logic blocks (each a look-up table plus a flip-flop) and programmable routing. You load a bitstream that sets every LUT's contents and every routing switch, configuring the blank silicon to behave like whatever digital circuit you designed, with no custom manufacturing.
What is a LUT (look-up table) in an FPGA?
A LUT is the basic logic element of an FPGA: a tiny truth table stored in SRAM. An
n-input LUT holds 2^n configuration bits, its inputs address those bits, and the addressed bit is the output. Because every bit is independently 0 or 1, an n-input LUT can be loaded to compute any function of n inputs, which is why it is the FPGA's universal building block.What is the difference between an FPGA and an ASIC?
An FPGA is reconfigurable: the same chip becomes a new circuit by loading a different bitstream, ideal for prototyping and low-to-medium volume. An ASIC (application-specific integrated circuit) is etched once with custom photomasks in a factory, so it is faster, denser, and cheaper per unit at high volume, but it can never be reprogrammed and a design error means a costly new mask set.
What is the difference between a PLA and a PAL?
Both implement sum-of-products logic with two planes of wires. A PLA (programmable logic array) has a programmable AND plane AND a programmable OR plane, so product terms can be freely shared across outputs. A PAL (programmable array logic) keeps the AND plane programmable but makes the OR plane fixed, so each output sums a fixed set of product terms; it is simpler, faster, and historically cheaper.
How does VHDL code end up running on an FPGA?
Through a tool flow: synthesis turns the HDL into gates and flip-flops, technology mapping packs that logic into the chip's LUTs and registers, place and route assigns each piece to a physical logic block and configures the routing, and bitstream generation emits a binary that sets every LUT and switch. Static timing analysis confirms the design meets setup and hold at the target clock, then the bitstream is loaded into the FPGA's SRAM and the chip runs your circuit.
That is the end of the chain this course set out to build: from a single switch, through gates, arithmetic, memory, an ALU, and a full 8-bit CPU, to HDL and the programmable silicon that runs it. The natural next step leaves the simulator: take a design like the CPU you built, write it in VHDL, verify it with a testbench, and load the bitstream onto a real FPGA board in Vivado or Quartus, where the switches you have been simulating all along finally run as physical hardware.
Every lesson here builds toward one thing: a working CPU, from the transistor up.
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