Memory
Circuits that remember. Feedback turns gates into latches and flip-flops, the storage cells that hold a bit until you change them, and the register that holds a whole byte.
The clock and sequential logicThe heartbeat that lets a circuit rememberEverything so far has been combinational: outputs depend only on the present inputs. Sequential logic adds memory, and a clock is the shared signal that tells every memory element when to update, so the whole machine changes in lockstep.How a circuit remembersThe one idea that turns logic into memoryFeeding an output back into an input lets a circuit hold a value after its inputs change, the single idea that turns logic into memory.Two kinds of circuitCombinational versus sequentialA combinational circuit's output depends only on current inputs; a sequential one also depends on stored history, and the difference tells you whether you need a clock.SR latchThe first memoryEvery combinational circuit forgets the moment its inputs change. The SR latch breaks that rule by feeding its output back into its own input, giving it a state that persists after the inputs return to zero.Gated D latchOne data input, one enableThe SR latch has a forbidden input combination and two inputs to manage. The gated D latch fixes both with a single Data line and an Enable gate. While EN is high the output follows D; when EN falls the last value is held.The transparency problemWhy a latch is not enoughA latch passes changes through the whole time it is enabled (transparent), so to capture a value at one precise instant you chain two latches into an edge-triggered flip-flop.D flip-flopMaster and slaveA D latch is transparent while enabled, which lets glitches on D corrupt the stored value. Chain two latches in opposite phases and you get a flip-flop: D is captured at exactly one instant, the rising clock edge, and held until the next one.Flip-flop types: D, JK, T, SRFour ways to clock a bit, and the tables that design themThe four standard edge-triggered flip-flops differ only in what their inputs mean: D loads a value, T toggles, JK does everything with no illegal input, and SR sets or resets but forbids both at once. Each is captured by a characteristic table (next state from the inputs) and an excitation table (the inputs a desired transition needs), and that excitation table is the tool you use to design sequential logic.JK flip-flopThe flip-flop with no illegal inputThe SR flip-flop can set or reset a bit but breaks if you assert both inputs at once. The JK flip-flop keeps set and reset (now called J and K) and turns that forbidden corner into a useful fourth operation: with J = K = 1 it toggles. So all four input combinations are legal (hold, reset, set, toggle), which made JK the universal flip-flop of the discrete-logic era.T flip-flopOne input that flips a bitA T (toggle) flip-flop has a single input: with T = 0 it holds its bit, and with T = 1 it flips the bit on every clock edge. Holding T = 1 makes the output a clean square wave at half the clock frequency, a divide-by-2, and chaining T flip-flops so each drives the next is exactly how a binary counter is built.Register bitA flip-flop with a write enableA bare flip-flop overwrites its stored value on every clock edge. A register bit adds a write enable so you can choose when to load new data and when to hold, using feedback from Q to itself.Widening a 1-bit circuitThe just replicate it patternTo handle a whole byte you place eight copies of a 1-bit circuit side by side sharing their control lines, the replicate-it pattern behind every multi-bit block.Shift registersMarching a bit along a chainA shift register is a row of flip-flops where each one's output feeds the next one's input, so on every clock edge the stored bits march one position along the chain. It moves data serially, converts between serial and parallel, and is the basis of the control unit's ring counter.Timing: delay and the clock speed limitWhy a chip can only be clocked so fastReal gates take time to switch, so a signal needs a moment to settle through a chain of logic. That propagation delay, summed along the slowest path between flip-flops, sets the minimum clock period: clock faster than the logic can settle and you capture wrong values.Metastability and synchronizersWhat happens when an input misses the setup windowSample a flip-flop while its input is changing and it can hang at an in-between voltage and resolve to 0 or 1 only after an unpredictable extra delay. The chance it is still undecided falls off exponentially with time, so the standard fix for an asynchronous input is a two-flip-flop synchronizer that gives the first flop a full clock period to settle before any logic sees it.Reset: starting from a known stateWhy every sequential circuit needs a resetA reset input forces flip-flops to a known value on power-up, because a circuit that starts in a random state is unpredictable; synchronous reset acts on the clock edge, asynchronous reset acts immediately.SRAM vs DRAMTwo ways to store a bit, and why both existSRAM stores each bit in a 6-transistor latch (fast, used for caches and registers) while DRAM stores it as charge on a tiny capacitor (dense and cheap but must be refreshed), which is why main memory is DRAM and caches are SRAM.ROM and PLA: logic as a lookupBuilding a function from memory instead of gatesAny combinational function is just its truth table, so you can build it as memory instead of gates: a ROM stores the output at every input address, a PLA stores only the product terms you actually need. This is how lookup tables and FPGAs work.The memory hierarchyRegisters, cache, RAM, and disk, from fastest to biggestFaster memory is smaller and costs more per bit, so a computer stacks several kinds: a few fast registers on top, then cache, then main memory (RAM), then huge slow disk. Locality lets a little fast memory in front of a lot of slow memory serve almost every access.