SR latch

Q: How does an SR latch store a bit?

Through feedback. Built from two NOR gates, each output drives the other gate's input. Pulsing S forces Q = 1, pulsing R forces Q = 0, and when both are 0 the loop simply re-asserts whatever it last settled to, holding the bit.

Q: Why must you never set S and R both to 1?

Raising S and R together forces both NOR outputs to 0, breaking the rule that Q and Qb are complements. When you release them, the latch races to an unpredictable value. The D latch removes this hazard.

The first memory

4 min read

An SR latch is the simplest memory element: cross-coupled gates feed each output back to the other's input, so the circuit holds its last state after the Set and Reset inputs return to 0. It is how a circuit first gains the ability to remember.

Builds onNOR

Build it in the lab →

Everything you have built so far is combinational: the output is a pure function of the present inputs, and the instant the inputs change the old answer is gone. A computer is mostly *memory*, so something has to break that rule. This lesson does, using two NOR gates and one new idea: feedback, wiring an output back into the circuit's own input. Watch that feedback hold a bit, step by step, in the interactive memory simulator.

Cross-coupled NOR gates

Take two NOR gates and connect them so each gate's output feeds the *other* gate's second input. Call the top output Q and the bottom output Qb (Q-bar, its complement). The settled state obeys:

Q = NOR(R, Qb)

Qb = NOR(S, Q)

R (Reset) feeds the top gate, S (Set) feeds the bottom one. When both S and R are 0, neither gate is forced from outside, so the loop simply holds whatever it already was. That is the hold state, and it is only possible because of the feedback wires.

Behavior over time

Start S=0, R=0, and suppose Q=0, Qb=1. Both gates agree: NOR(0,1)=0 gives Q, NOR(0,0)=1 gives Qb. Stable.
Pulse S=1 (set): the bottom gate sees a 1, forcing Qb=0. Now the top gate sees R=0, Qb=0, so Q=1. The bit flipped to 1.
Drop S=0 (hold): inputs are 0,0 again, but now Q=1, Qb=0. Check: NOR(0,0)=1 keeps Q, NOR(0,1)=0 keeps Qb. Q holds 1 with S gone.
Pulse R=1 (reset): the top gate sees a 1, forcing Q=0. The bottom gate then sees S=0, Q=0, so Qb=1. The bit flipped back to 0.
Drop R=0 (hold): Q=0, Qb=1 again, same as the start. It holds 0.

Steps 3 and 5 both have S=0, R=0, yet Q=1 in one and Q=0 in the other. Identical inputs, different outputs, decided by history. That is exactly what memory means in hardware.

Never raise S and R to 1 together. Both NOR outputs would be forced to 0, breaking the rule that Q and Qb are complements, and when you release them the latch races to an unpredictable value. The next lesson removes this hazard entirely.

A concrete picture: an SR latch is a light with two push-buttons, one marked SET (on) and one marked RESET (off). Tap SET and the light comes on and *stays* on after you let go; tap RESET and it goes off and stays off. The buttons only nudge it; the light remembers. Mashing both at once is the forbidden state, the light cannot be on and off together.

Cross-coupled NOR SR latch. Open it in the lab and trace the feedback: Q runs back into the R gate, Qb back into the S gate.

Try it

In the lab, set S = 1 briefly then drop it back to 0. What is Q? Now without touching S or R (both 0), does Q change? Why?

This one feedback path is the seed of all stored state. From here you will tame its interface (D latch), make it update only on a clock edge (D flip-flop), and add a write enable (register bit) until you have the cell that builds your CPU's accumulator and registers.

Spot the fault

S0R0Q~Qb~

Look at Q

Oscillation (~)

S and R were both raised to 1 (the forbidden state) and released at the same instant. With no asymmetry to break the tie, the cross-coupled NOR gates chase each other and the outputs oscillate (~) instead of settling. Never assert S and R together.

Frequently asked

What is an SR latch?

An SR latch is the simplest memory element: two cross-coupled gates feed each output back into the other's input, so the circuit holds its last state after the Set and Reset inputs return to 0.

How does an SR latch store a bit?

Through feedback. Built from two NOR gates, each output drives the other gate's input. Pulsing S forces Q = 1, pulsing R forces Q = 0, and when both are 0 the loop simply re-asserts whatever it last settled to, holding the bit.

Why must you never set S and R both to 1?

Raising S and R together forces both NOR outputs to 0, breaking the rule that Q and Qb are complements. When you release them, the latch races to an unpredictable value. The D latch removes this hazard.

What is the difference between a latch and a flip-flop?

A latch (like the SR or D latch) is level-sensitive: it responds while its control input is held at a level. A flip-flop is edge-triggered: it captures its input at one instant, the clock edge, and ignores it the rest of the cycle.

You've got the theory. Now build it from scratch and watch it work.

Build it in the lab →

Builds towardGated D latch Flip-flop types: D, JK, T, SR JK flip-flop Reset: starting from a known state